Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BU2708AX
GENERAL DESCRIPTION
High voltage, high speed switching npn transistor in a plastic full-pack envelope. Intended for use in horizontal
deflection circuits of colour television receivers. Features exceptional tolerance to base drive and collector current
load variations, resulting in a low worst-case dissipation. Designed to withstand V
CES
pulses up to 1700 V.
QUICK REFERENCE DATA
SYMBOL
V
CESM
V
CEO
I
C
I
CM
P
tot
V
CEsat
I
Csat
t
s
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Total power dissipation
Collector-emitter saturation voltage
Collector saturation current
Storage time
CONDITIONS
V
BE
= 0 V
TYP.
-
-
-
-
-
-
4
4.8
MAX.
1700
825
8
15
45
1.0
-
5.5
UNIT
V
V
A
A
W
V
A
µs
T
hs
≤
25 ˚C
I
C
= 4 A; I
B
= 1.33 A
f = 16 kHz
I
Csat
= 4 A; f = 16 kHz
PINNING - SOT399
PIN
1
2
3
base
collector
emitter
DESCRIPTION
PIN CONFIGURATION
case
SYMBOL
c
b
1 2 3
case isolated
e
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
V
CESM
V
CEO
I
C
I
CM
I
B
I
BM
-I
BM
P
tot
T
stg
T
j
PARAMETER
Collector-emitter voltage peak value
Collector-emitter voltage (open base)
Collector current (DC)
Collector current peak value
Base current (DC)
Base current peak value
Reverse base current peak value
1
Total power dissipation
Storage temperature
Junction temperature
CONDITIONS
V
BE
= 0 V
MIN.
-
-
-
-
-
-
-
-
-65
-
MAX.
1700
825
8
15
4
6
5
45
150
150
UNIT
V
V
A
A
A
A
A
W
˚C
˚C
T
hs
≤
25 ˚C
ESD LIMITING VALUES
SYMBOL
V
C
PARAMETER
CONDITIONS
MIN.
-
MAX.
10
UNIT
kV
Electrostatic discharge capacitor voltage Human body model (250 pF,
1.5 kΩ)
1
Turn-off current.
September 1997
1
Rev 1.100
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BU2708AX
THERMAL RESISTANCES
SYMBOL
R
th j-hs
R
th j-hs
R
th j-a
PARAMETER
Junction to heatsink
Junction to heatsink
Junction to ambient
CONDITIONS
without heatsink compound
with heatsink compound
in free air
TYP.
-
-
35
MAX.
3.7
2.8
-
UNIT
K/W
K/W
K/W
ISOLATION LIMITING VALUE & CHARACTERISTIC
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
V
isol
PARAMETER
Repetitive peak voltage from all
three terminals to external
heatsink
CONDITIONS
R.H.
≤
65 % ; clean and dustfree
MIN.
-
TYP.
MAX.
2500
UNIT
V
C
isol
Capacitance from T2 to external f = 1 MHz
heatsink
-
22
-
pF
STATIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
I
CES
I
CES
I
EBO
BV
EBO
V
CEOsust
V
CEsat
V
BEsat
h
FE
h
FE
PARAMETER
Collector cut-off current
2
Emitter cut-off current
Emitter-base breakdown voltage
Collector-emitter sustaining voltage
Collector-emitter saturation voltage
Base-emitter saturation voltage
DC current gain
CONDITIONS
V
BE
= 0 V; V
CE
= V
CESMmax
V
BE
= 0 V; V
CE
= V
CESMmax
;
T
j
= 125 ˚C
V
EB
= 6 V; I
C
= 0 A
I
B
= 1 mA
I
B
= 0 A; I
C
= 100 mA;
L = 25 mH
I
C
= 4 A; I
B
= 1.33 A
I
C
= 4 A; I
B
= 1.33 A
I
C
= 100 mA; V
CE
= 5 V
I
C
= 4 A; V
CE
= 1 V
MIN.
-
-
-
7.5
825
-
0.83
-
3
TYP.
-
-
-
13.5
900
-
0.91
21
6
MAX.
1.0
2.0
70
-
-
1.0
1.00
-
7.3
UNIT
mA
mA
µA
V
V
V
V
DYNAMIC CHARACTERISTICS
T
hs
= 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
Switching times (line deflection
circuit 16 kHz)
t
s
t
f
Turn-off storage time
Turn-off fall time
CONDITIONS
I
Csat
= 4 A; I
B(end)
= 0.8 A; -I
BM
= I
CM
/2;
L
B
= 6
µH;
-V
BB
= 4 V; L
C
= 1 mH;
C
FB
= 12.2 nF
TYP.
MAX.
UNIT
4.8
0.4
5.5
0.52
µs
µs
2
Measured with half sine-wave voltage (curve tracer).
September 1997
2
Rev 1.100
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BU2708AX
ICsat
+ 50v
100-200R
IC
90 %
Horizontal
tf
10 %
Oscilloscope
IB
t
ts
IBend
Vertical
100R
6V
30-60 Hz
1R
t
- IBM
Fig.1. Test circuit for V
CEOsust
.
Fig.4. Switching times definitions.
IC / mA
+ 150 v nominal
adjust for ICsat
Lc
250
200
100
IBend
LB
T.U.T.
Cfb
0
VCE / V
min
VCEOsust
-VBB
Fig.2. Oscilloscope display for V
CEOsust
.
Fig.5. Switching times test circuit.
TRANSISTOR
IC
DIODE
ICsat
100
hFE
VCE = 5 V
BU2708AF
Ths = 25 C
Ths = 85 C
t
IB
IBend
t
20us
26us
64us
10
VCE
1
0.01
0.1
1
10
IC / A
100
t
Fig.3. Switching times waveforms.
Fig.6. DC current gain. h
FE
= f (I
C
)
Parameter T
hs
(Low and high gain)
September 1997
3
Rev 1.100
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BU2708AX
hFE
100
VCE = 1 V
BU2708AF
10
PTOT / W
IC = 3.5 A
f = 16 kHz
Tj = 85 C
BU2708AF/DF
Ths = 25 C
Ths = 85 C
10
1
0.01
0.1
1
10
IC / A
100
1
0
0.5
1
1.5
IB / A
2
Fig.7. DC current gain. h
FE
= f (I
C
)
Parameter T
hs
(Low and high gain)
Fig.10. Limit P
tot
; T
j
= 85˚C
P
tot
= f (I
B(end)
); I
C
= 3.5 A; f = 16 kHz
VCEsat / V
10
Tj = 85 C
Tj = 25 C
BU2708AF
10
PTOT / W
IC = 4 A
f = 16 kHz
Tj = 85 C
BU2708AF/DF
1
IC/IB = 8
IC/IB = 4
0.1
0.01
0.1
1
10
IC / A
100
1
0
0.5
1
1.5
IB / A
2
Fig.8. Typical collector-emitter saturation voltage.
V
CEsat
= f (I
C
); parameter I
C
/I
B
Fig.11. Limit P
tot
; T
j
= 85˚C
P
tot
= f (I
B(end)
); I
C
= 4.0 A; f = 16 kHz
VBEsat / V
1.2
Tj = 85 C
Tj = 25 C
IC = 4A
1
BU2708AF
ts/tf / us
10
BU2708AF/DF
1.1
8
6
0.9
4
0.8
3A
0.7
IC = 4A
IC = 3.5A
2
0.6
0
0.5
1
1.5
IB / A
2
0
0
0.5
1
1.5
IB / A
2
Fig.9. Typical base-emitter saturation voltage.
V
BEsat
= f (I
B
); parameter I
C
Fig.12. Limit storage and fall time.
t
s
= f (I
B
); tf = f (I
B
); parameter I
C
; T
j
= 85˚C; f = 16 kHz
September 1997
4
Rev 1.100
Philips Semiconductors
Product specification
Silicon Diffused Power Transistor
BU2708AX
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
with heatsink compound
VCC
LC
IBend
VCL
LB
T.U.T.
CFB
-VBB
0
20
40
60
80
Ths / C
100
120
140
Fig.13. Normalised power dissipation.
PD% = 100⋅PD/PD 25˚C = f (T
hs
)
Fig.15. Test Circuit RBSOA. V
CC
= 150 V;
-V
BB
= 1 - 4 V;
L
C
= 1 mH; V
CL
= 1500 V; L
B
= 1 - 3
µH;
C
FB
= 1 - 4 nF; I
B(end)
= 0.8 - 4 A
Zth / K/W
10
BU2708AF/DF
16
14
0.5
0.2
0.1
0.05
0.02
t
p
D=
T
T
t
IC / A
BU2708AF/DF
1
12
10
8
6
P
D
t
p
Area where
Fails occur
0.1
0.01
D= 0
0.001
1.0E-06
1E-04
4
2
0
100
VCE / V
1000
1700
1E-02
tp / sec
1E+00
Fig.14. Transient thermal impedance.
Z
th j-hs
= f(t); parameter D = t
p
/T
Fig.16. Reverse bias safe operating area. T
j
≤
T
jmax
September 1997
5
Rev 1.100
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