PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4481162, 4481182, 4481322, 4481362
8M-BIT ZEROSB
TM
SRAM
PIPELINED OPERATION
Description
The
µ
PD4481162 is a 524,288-word by 16-bit, the
µ
PD4481182 is a 524,288-word by 18-bit, the
µ
PD4481322 is a
262,144-word by 32-bit and the
µ
PD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with
advanced CMOS technology using full CMOS six-transistor memory cell.
The
µ
PD4481162,
µ
PD4481182,
µ
PD4481322 and
µ
PD4481362 are optimized to eliminate dead cycles for read to
write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The
µ
PD4481162,
µ
PD4481182,
µ
PD4481322 and
µ
PD4481362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The
µ
PD4481162,
µ
PD4481182,
µ
PD4481322 and
µ
PD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness or 165-pin TAPE FBGA for high density and low capacitive loading.
Features
•
Low voltage core supply (A version : V
DD
= 3.3 ± 0.165V, C version : V
DD
= 2.5 ± 0.125V)
•
Synchronous operation
•
100 percent bus utilization
•
Internally self-timed write control
•
Burst read / write : Interleaved burst and linear burst sequence
•
Fully registered inputs and outputs for pipelined operation
•
All registers triggered off positive clock edge
•
3.3V or 2.5V LVTTL Compatible : All inputs and outputs
•
Fast clock access time : 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)
•
Asynchronous output enable : /G
•
Burst sequence selectable : MODE
•
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
•
Separate byte write enable : /BW1 - /BW4 (
µ
PD4481322 and
µ
PD4481362), /BW1 - /BW2 (
µ
PD4481162 and
µ
PD4481182)
•
Three chip enables for easy depth expansion
•
Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15562EJ1V0DS00 (1st edition)
Date Published June 2001 NS CP(K)
Printed in Japan
©
2001
µ
PD4481162, 4481182, 4481322, 4481362
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
200
167
133
3.3 ± 0.165
3.3 V or 2.5 V
LVTTL
165-pin TAPE FBGA
(13 x 15)
2.5 ± 0.125
2.5 V
LVTTL
Core Supply
Voltage
V
3.3 ± 0.165
3.3 V or 2.5 V
LVTTL
100-pin PLASTIC LQFP
(14 x 20)
I/O Interface
Package
(1/2)
µ
PD4481162GF-A50
µ
PD4481162GF-A60
µ
PD4481162GF-A75
µ
PD4481182GF-A50
µ
PD4481182GF-A60
µ
PD4481182GF-A75
µ
PD4481322GF-A50
µ
PD4481322GF-A60
µ
PD4481322GF-A75
µ
PD4481362GF-A50
µ
PD4481362GF-A60
µ
PD4481362GF-A75
µ
PD4481162GF-C50
µ
PD4481162GF-C60
µ
PD4481162GF-C75
µ
PD4481182GF-C50
µ
PD4481182GF-C60
µ
PD4481182GF-C75
µ
PD4481322GF-C50
µ
PD4481322GF-C60
µ
PD4481322GF-C75
µ
PD4481362GF-C50
µ
PD4481362GF-C60
µ
PD4481362GF-C75
µ
PD4481162F9-A50-EQx
µ
PD4481162F9-A60-EQx
µ
PD4481162F9-A75-EQx
µ
PD4481182F9-A50-EQx
µ
PD4481182F9-A60-EQx
µ
PD4481182F9-A75-EQx
µ
PD4481322F9-A50-EQx
µ
PD4481322F9-A60-EQx
µ
PD4481322F9-A75-EQx
µ
PD4481362F9-A50-EQx
µ
PD4481362F9-A60-EQx
µ
PD4481362F9-A75-EQx
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
Remark
"EQx" of part number is package specifications. However, this is not available.
2
Preliminary Data Sheet M15562EJ1V0DS
µ
PD4481162, 4481182, 4481322, 4481362
(2/2)
Part number
Access
Time
ns
Clock
Frequency
MHz
200
167
133
200
167
133
200
167
133
200
167
133
Core Supply
Voltage
V
2.5 ± 0.125
2.5 V
LVTTL
165-pin TAPE FBGA
(13 x 15)
I/O Interface
Package
µ
PD4481162F9-C50-EQx
µ
PD4481162F9-C60-EQx
µ
PD4481162F9-C75-EQx
µ
PD4481182F9-C50-EQx
µ
PD4481182F9-C60-EQx
µ
PD4481182F9-C75-EQx
µ
PD4481322F9-C50-EQx
µ
PD4481322F9-C60-EQx
µ
PD4481322F9-C75-EQx
µ
PD4481362F9-C50-EQx
µ
PD4481362F9-C60-EQx
µ
PD4481362F9-C75-EQx
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
3.2
3.5
4.2
Remark
"EQx" of part number is package specifications. However, this is not available.
Preliminary Data Sheet M15562EJ1V0DS
3
µ
PD4481162, 4481182, 4481322, 4481362
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-pin PLASTIC LQFP (14
×
20)
[
µ
PD4481162GF,
µ
PD4481182GF]
/BW2
/BW1
/CKE
/CE2
ADV
CE2
CLK
/WE
A17
V
DD
V
SS
/CE
NC
NC
NC
A6
A7
A8
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
V
DD
V
DD
V
DD
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
V
DD
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
MODE
A5
A4
A3
A2
A1
A0
V
SS
NC
NC
V
DD
A10
A11
A12
A13
A14
A15
Remark
Refer to
Package Drawings
for 1-pin index mark.
4
Preliminary Data Sheet M15562EJ1V0DS
A16
NC
NC
A9
/G
µ
PD4481162, 4481182, 4481322, 4481362
Pin Identifications
[
µ
PD4481162GF,
µ
PD4481182GF]
Symbol
A0 - A18
Pin No.
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
44, 45, 46, 47, 48, 49, 50, 83, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,
18, 19, 22, 23
I/OP1, NC
Note
I/OP2, NC
Note
ADV
/CE, CE2, /CE2
/WE
/BW1, /BW2
/G
CLK
/CKE
MODE
74
24
85
98, 97, 92
88
93, 94
86
89
87
31
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
Synchronous / Asynchronous Data Out (Parity)
Synchronous Address Load / Advance Input
Synchronous Chip Enable Input
Synchronous Write Enable Input
Synchronous Byte Write Enable Input
Asynchronous Output Enable Input
Clock Input
Synchronous Clock Enable Input
Asynchronous Burst Sequence Select Input
Have to tied to V
DD
or V
SS
during normal operation
ZZ
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
64
14, 15, 16, 41, 65, 66, 91
17, 40, 67, 90
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Asynchronous Power Down State Input
Power Supply
Ground
Output Buffer Power Supply
Output Buffer Ground
Description
Synchronous Address Input
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection
51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96
Note
NC (No Connection) is used in the
µ
PD4481162GF.
I/OP1 - I/OP2 are used in the
µ
PD4481182GF.
Preliminary Data Sheet M15562EJ1V0DS
5
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