DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4516421A, 4516821A, 4516161A for Rev.P
16M-bit Synchronous DRAM
2-banks, LVTTL
(2
Description
Features
•
Pulsed interface
• ×4, ×8, ×16
organization
Document No. E0122N10 (Ver.1.0)
(Previous No. M12939EJ3V0DS00)
Date Published May 2001 CP (K)
Printed in Japan
The
µ
PD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 44-pin TSOP (II) (× 4,
×
8) and 50-pin TSOP (II) (× 16).
memories, organized as 2,097,152
×
4
×
2, 1,048,576
×
8
×
2, 524,288
×
16
×
2 (word
×
bit
×
bank), respectively.
•
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
•
Possible to assert random column address in every cycle
•
Dual internal banks controlled by A11(Bank Select)
•
Byte control (×16) by LDQM and UDQM
•
Programmable Wrap sequence (Sequential / Interleave)
•
Programmable burst length (1, 2, 4, 8 and full page)
•
Programmable /CAS latency (2 and 3)
•
CBR (Auto) refresh and self refresh
•
Single 3.3 V
±
0.3 V power supply
•
2,048 refresh cycles / 32 ms
•
Automatic precharge and controlled precharge
•
LVTTL compatible inputs and outputs
•
Burst termination by Burst stop command and Precharge command
/
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
R
3U
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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