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UPD44164362F5-E30-EQ1: 产品描述DDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165; 产品类别存储存储; 文件大小211KB，共32页; 制造商NEC(日电)

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UPD44164362F5-E30-EQ1概述

DDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165

UPD44164362F5-E30-EQ1规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
零件包装代码	BGA
包装说明	BGA,
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.A
最长访问时间	0.27 ns
其他特性	PIPELINED ARCHITECTURE
JESD-30 代码	R-PBGA-B165
JESD-609代码	e0
长度	15 mm
内存密度	18874368 bit
内存集成电路类型	DDR SRAM
内存宽度	36
功能数量	1
端子数量	165
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
组织	512KX36
封装主体材料	PLASTIC/EPOXY
封装代码	BGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY
并行/串行	PARALLEL
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
端子面层	TIN LEAD
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	13 mm
Base Number Matches	1

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PRELIMINARY DATA SHEET

PD44164082, 44164182, 44164362

18M-BIT DDRII SRAM

2-WORD BURST OPERATION

MOS INTEGRATED CIRCUIT

Description

The

PD44164082 is a 2,097,152-word by 8-bit, the

PD44164182 is a 1,048,576-word by 18-bit and the

PD44164362

is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using

full CMOS six-transistor memory cell.

The

PD44164082,

PD44164182 and

PD44164362 integrates unique synchronous peripheral circuitry and a burst

counter. All input registers controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K.

These products are suitable for applications which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

•

1.8 ± 0.1 V power supply and HSTL I/O

•

DLL circuitry for wide output data valid window and future frequency scaling

•

Pipelined double data rate operation

•

Common data input/output bus

•

Two-tick burst for low DDR transaction size

•

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

•

Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

•

Internally self-timed write control

•

Clock-stop capability with

s restart

•

User programmable impedence output

•

Fast clock cycle time : 3.0 ns (333 MHz), 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz)

•

Simple control logic for easy depth expansion

•

JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15821EJ2V0DS00 (2nd edition)

Date Published April 2002 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2001

UPD44164362F5-E30-EQ1相似产品对比

	UPD44164362F5-E30-EQ1	UPD44164082F5-E30-EQ1	UPD44164182F5-E33-EQ1	UPD44164082F5-E33-EQ1	UPD44164182F5-E30-EQ1
描述	DDR SRAM, 512KX36, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	DDR SRAM, 2MX8, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	DDR SRAM, 1MX18, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	DDR SRAM, 2MX8, 0.29ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	DDR SRAM, 1MX18, 0.27ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
是否无铅	含铅	含铅	含铅	含铅	含铅
是否Rohs认证	不符合	不符合	不符合	不符合	不符合
零件包装代码	BGA	BGA	BGA	BGA	BGA
包装说明	BGA,	BGA,	BGA,	BGA,	BGA,
针数	165	165	165	165	165
Reach Compliance Code	compliant	compliant	compliant	compliant	compli
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Base Number Matches	1	1	1	-	-

UPD44164362F5-E30-EQ1

UPD44164362F5-E30-EQ1概述

UPD44164362F5-E30-EQ1规格参数

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UPD44164362F5-E30-EQ1相似产品对比

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