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CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
72-Mbit QDR
®
II+ SRAM 4-Word Burst Architecture
(2.5 Cycle Read Latency) with ODT
72-Mbit QDR
®
II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■
Configurations
With Read Cycle Latency of 2.5 cycles
CY7C2561KV18 – 8M x 8
CY7C2576KV18 – 8M x 9
CY7C2563KV18 – 4M x 18
CY7C2565KV18 – 2M x 36
Separate independent read and write data ports
❐
Supports concurrent transactions
550 MHz clock for high bandwidth
4-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces on both read and write
ports (data transferred at 1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
On-Die Termination (ODT) feature
❐
Supported for D
[x:0]
, BWS
[x:0]
, and K/K inputs
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR
®
II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in x8, x9, x18, and x36 configurations
Full data coherency, providing most current data
Core V
DD
= 1.8V± 0.1V; I/O V
DDQ
= 1.4V to V
DD [1]
❐
Supports both 1.5V and 1.8V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
■
■
■
■
■
Functional Description
The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and
CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II archi-
tecture, QDR II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit
words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that
burst sequentially into or out of the device. Because data is trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
These devices have an On-Die Termination feature supported
for D
[x:0]
, BWS
[x:0]
, and K/K inputs, which helps eliminate
external termination resistors, reduce cost, reduce board area,
and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Table 1. Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
550 MHz
550
900
900
920
1310
500 MHz
500
830
830
850
1210
450 MHz
450
760
760
780
1100
400 MHz
400
690
690
710
1000
Unit
MHz
mA
x8
x9
x18
x36
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4V to V
DD
.
Cypress Semiconductor Corporation
Document Number: 001-15887 Rev. *K
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2010
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CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Logic Block Diagram (CY7C2561KV18)
8
D
[7:0]
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Address
Register
Address
Register
21
A
(20:0)
2M x 8 Array
2M x 8 Array
2M x 8 Array
2M x 8 Array
K
K
CLK
Gen.
RPS
Control
Logic
DOFF
Read Data Reg.
CQ
32
V
REF
WPS
NWS
[1:0]
Control
Logic
16
16
Reg.
Reg.
Reg. 8
8
8
8
CQ
8
Q
[7:0]
QVLD
Logic Block Diagram (CY7C2576KV18)
D
[8:0]
9
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(20:0)
21
Address
Register
Address
Register
21
A
(20:0)
2M x 9 Array
2M x 9 Array
2M x 9 Array
2M x 9 Array
K
K
CLK
Gen.
RPS
Control
Logic
DOFF
Read Data Reg.
CQ
36
V
REF
WPS
BWS
[0]
Control
Logic
18
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q
[8:0]
QVLD
Document Number: 001-15887 Rev. *K
Page 2 of 30
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CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Logic Block Diagram (CY7C2563KV18)
D
[17:0]
18
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(19:0)
20
Address
Register
Address
Register
20
A
(19:0)
1M x 18 Array
1M x 18 Array
1M x 18 Array
1M x 18 Array
K
K
CLK
Gen.
RPS
Control
Logic
DOFF
Read Data Reg.
CQ
72
V
REF
WPS
BWS
[1:0]
Control
Logic
36
36
Reg.
Reg.
Reg. 18
18
18
18
CQ
18
Q
[17:0]
QVLD
Logic Block Diagram (CY7C2565KV18)
D
[35:0]
36
Write
Reg
Write
Reg
Write
Reg
Write
Reg
Read Add. Decode
Write Add. Decode
A
(18:0)
19
Address
Register
Address
Register
19
A
(18:0)
512K x 36 Array
512K x 36 Array
512K x 36 Array
512K x 36 Array
K
K
CLK
Gen.
RPS
Control
Logic
DOFF
Read Data Reg.
CQ
144
V
REF
WPS
BWS
[3:0]
Control
Logic
72
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q
[35:0]
QVLD
Document Number: 001-15887 Rev. *K
Page 3 of 30
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CY7C2561KV18, CY7C2576KV18
CY7C2563KV18, CY7C2565KV18
Contents
72-Mbit QDR
®
II+ SRAM 4-Word Burst Architecture
(2.5 Cycle Read Latency) with ODT ................................ 1
Features ............................................................................. 1
Configurations .................................................................. 1
Functional Description ..................................................... 1
Logic Block Diagram (CY7C2561KV18) .......................... 2
Logic Block Diagram (CY7C2576KV18) .......................... 2
Logic Block Diagram (CY7C2563KV18) .......................... 3
Logic Block Diagram (CY7C2565KV18) .......................... 3
Contents ............................................................................ 4
Pin Configuration ............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD) ...................................... 10
On-Die Termination (ODT) ........................................ 10
PLL ............................................................................ 10
Application Example ...................................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Power Up Sequence in QDR II+ SRAM ......................... 21
Power Up Sequence ................................................. 21
PLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Neutron Soft Error Immunity ......................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Read/Write/Deselect Sequence ................................ 26
Ordering Information ...................................................... 27
Package Diagram ............................................................ 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 001-15887 Rev. *K
Page 4 of 30
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