DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44324082, 44324092, 44324182, 44324362
36M-BIT DDR II SRAM
2-WORD BURST OPERATION
Description
The
μ
PD44324082 is a 4,194,304-word by 8-bit, the
μ
PD44324092 is a 4,194,304-word by 9-bit, the
μ
PD44324182 is a
2,097,152-word by 18-bit and the
μ
PD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44324082,
μ
PD44324092,
μ
PD44324182 and
μ
PD44324362 integrate unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high
density and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
•
1.8 ± 0.1 V power supply
•
165-pin PLASTIC BGA package (13 x 15)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Pipelined double data rate operation
•
Common data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
•
User programmable impedance output
•
Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG boundary scan
<R>
•
Operating ambient temperature: Commercial T
A
= 0 to +70°C
Industrial
T
A
= –40 to +85°C
(-E37, -E40, -E50)
(-E40Y, -E50Y)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16780EJ4V0DS00 (4th edition)
Date Published March 2007 NS CP(N)
Printed in Japan
The mark <R> shows major revised points.
2003
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μ
PD44324082, 44324092, 44324182, 44324362
Pin Configurations
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44324082]
4M x 8-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DD
Q
NC
NC
NC
NC
NC
DQ7
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
NW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
A
DQ0 to DQ7
LD#
R, W#
NW0#, NW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Nibble Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL/PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
2A of this product can also be used as NC.
4
Data Sheet M16780EJ4V0DS
μ
PD44324082, 44324092, 44324182, 44324362
165-pin PLASTIC BGA (13 x 15)
(Top View)
[
μ
PD44324092]
4M x 9-bit
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ5
NC
DQ6
V
DD
Q
NC
NC
NC
NC
NC
DQ8
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
NC
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
A
DQ0 to DQ8
LD#
R, W#
BW0#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
: Address inputs
: Data inputs / outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: DLL/PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
Remarks 1.
×××#
indicates active LOW signal.
2.
Refer to
Package Drawing
for the index mark.
3.
2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.
2A of this product can also be used as NC.
Data Sheet M16780EJ4V0DS
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
