Datasheet
μ
PD44324185B
μ
PD44324365B
36M-BIT DDR II SRAM SEPARATE I/O
2-WORD BURST OPERATION
Description
The
μ
PD44324185B is a 2,097,152-word by 18-bit and the
μ
PD44324365B is a 1,048,576-word by 36-bit
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-
transistor memory cell.
The
μ
PD44324185B and
μ
PD44324365B integrate unique synchronous peripheral circuitry and a burst
counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive edge of K
and K#. These products are suitable for application which require synchronous operation, high speed, low
voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA.
R10DS0037EJ0200
Rev.2.00
September 12, 2011
Features
•
1.8
±
0.1 V power supply
•
165-pin PLASTIC BGA (15 x 17)
•
HSTL interface
•
PLL circuitry for wide output data valid window and future frequency scaling
•
Separate independent read and write data ports
•
DDR read or write operation initiated each cycle
•
Pipelined double data rate operation
•
Separate data input/output bus
•
Two-tick burst for low DDR transaction size
•
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
•
Two output clocks (C and C#) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
•
Internally self-timed write control
•
Clock-stop capability. Normal operation is restored in 20
μ
s after clock is resumed.
•
User programmable impedance output (35 to 70
Ω)
•
Fast clock cycle time : 3.3 ns (300 MHz), 3.5 ns (287 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
•
Simple control logic for easy depth expansion
•
JTAG 1149.1 compatible test access port
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 1 of 34
μ
PD44324185B,
μ
PD44324365B
Ordering Information
Part No.
Organization
(word x bit)
2M x 18
Cycle
time
3.3ns
3.5ns
4.0ns
5.0ns
1M x 36
3.3ns
3.5ns
4.0ns
5.0ns
2M x 18
3.3ns
3.5ns
4.0ns
5.0ns
1M x 36
3.3ns
3.5ns
4.0ns
5.0ns
2M x 18
3.3ns
3.5ns
4.0ns
5.0ns
1M x 36
3.3ns
3.5ns
4.0ns
5.0ns
2M x 18
3.3ns
3.5ns
4.0ns
5.0ns
1M x 36
3.3ns
3.5ns
4.0ns
5.0ns
Clock
frequency
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
300MHz
287MHz
250MHz
200MHz
Ta =
−40
to 85°C
165-pin
PLASTIC BGA
(15 x 17)
Lead
Ta =
−40
to 85°C
165-pin
PLASTIC BGA
(15 x 17)
Lead-free
Ta = 0 to 70°C
165-pin
PLASTIC BGA
(15 x 17)
Lead
Operating Ambient
Temperature
Ta = 0 to 70°C
Package
165-pin
PLASTIC BGA
(15 x 17)
Lead-free
μ
PD44324185BF5-E33-FQ1-A
μ
PD44324185BF5-E35-FQ1-A
μ
PD44324185BF5-E40-FQ1-A
μ
PD44324185BF5-E50-FQ1-A
μ
PD44324365BF5-E33-FQ1-A
μ
PD44324365BF5-E35-FQ1-A
μ
PD44324365BF5-E40-FQ1-A
μ
PD44324365BF5-E50-FQ1-A
μ
PD44324185BF5-E33-FQ1
μ
PD44324185BF5-E35-FQ1
μ
PD44324185BF5-E40-FQ1
μ
PD44324185BF5-E50-FQ1
μ
PD44324365BF5-E33-FQ1
μ
PD44324365BF5-E35-FQ1
μ
PD44324365BF5-E40-FQ1
μ
PD44324365BF5-E50-FQ1
μ
PD44324185BF5-E33Y-FQ1-A
μ
PD44324185BF5-E35Y-FQ1-A
μ
PD44324185BF5-E40Y-FQ1-A
μ
PD44324185BF5-E50Y-FQ1-A
μ
PD44324365BF5-E33Y-FQ1-A
μ
PD44324365BF5-E35Y-FQ1-A
μ
PD44324365BF5-E40Y-FQ1-A
μ
PD44324365BF5-E50Y-FQ1-A
μ
PD44324185BF5-E33Y-FQ1
μ
PD44324185BF5-E35Y-FQ1
μ
PD44324185BF5-E40Y-FQ1
μ
PD44324185BF5-E50Y-FQ1
μ
PD44324365BF5-E33Y-FQ1
μ
PD44324365BF5-E35Y-FQ1
μ
PD44324365BF5-E40Y-FQ1
μ
PD44324365BF5-E50Y-FQ1
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 2 of 34
μ
PD44324185B,
μ
PD44324365B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44324185B]
2M x 18
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/144M
3
A
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
A
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW1#
NC
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
NC/288M
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
A
10
V
SS
/72M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
A
D0 to D17
Q0 to Q17
LD#
R, W#
BW0#, BW1#
K, K#
C, C#
CQ, CQ#
ZQ
DLL#
Remarks 1.
2.
3.
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
: PLL disable
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
NC/xxM
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
: Expansion address for xxMb
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 7A and 10A are expansion addresses : 10A for 72Mb
: 10A and 2A for 144Mb
: 10A, 2A and 7A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 3 of 34
μ
PD44324185B,
μ
PD44324365B
Pin Arrangement
165-pin PLASTIC BGA (15 x 17)
(Top View)
[
μ
PD44324365B]
1M x 36
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
Q27
D27
D28
Q29
Q30
D30
DLL#
D31
Q32
Q33
D33
D34
Q35
TDO
2
3
4
R, W#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
5
BW2#
BW3#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K#
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C#
7
BW1#
BW0#
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD#
A
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
A
A
9
A
D17
D16
Q16
Q15
D14
Q13
V
DD
Q
D12
Q12
D11
D10
Q10
Q9
A
10
V
SS
/144M
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
V
SS
/288M NC/72M
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
D18
D19
Q19
Q20
D21
Q22
V
DD
Q
D23
Q23
D24
D25
Q25
Q26
A
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
A
D0 to D35
Q0 to Q35
LD#
R, W#
BW0# to BW3#
K, K#
C, C#
CQ, CQ#
ZQ
Remarks 1.
2.
3.
: Address inputs
: Data inputs
: Data outputs
: Synchronous load
: Read Write input
: Byte Write data select
: Input clock
: Output clock
: Echo clock
: Output impedance matching
DLL#
TMS
TDI
TCK
TDO
V
REF
V
DD
V
DD
Q
V
SS
NC
: PLL disable
: IEEE 1149.1 Test input
: IEEE 1149.1 Test input
: IEEE 1149.1 Clock input
: IEEE 1149.1 Test output
: HSTL input reference input
: Power Supply
: Power Supply
: Ground
: No connection
×××#
indicates active LOW.
Refer to
Package Dimensions
for the index mark.
2A, 3A and 10A are expansion addresses: 3A for 72Mb
: 3A and 10A for 144Mb
: 3A, 10A and 2A for 288Mb
2A and 10A of this product can also be used as NC.
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 4 of 34
μ
PD44324185B,
μ
PD44324365B
Pin Description
(1/2)
Symbol
A
Type
Input
Description
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of K. All transactions operate on a burst of two words (one
clock period of bus activity). These inputs are ignored when device is deselected, i.e., NOP
(LD# = HIGH).
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See
Pin Arrangement
for ball site location of
individual signals.
x18 device uses D0 to D17.
x36 device uses D0 to D35.
Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K
and K# rising edges if C and C# are tied HIGH. Data is output in synchronization with C and
C# (or K and K#), depending on the LD# and R, W# command. See
Pin Arrangement
for
ball site location of individual signals.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and read/write direction. All transactions operate on a burst
of 2 data (one clock period of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type
(READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W#
must meet the setup and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written during WRITE cycles. These signals must meet setup and hold times
around the rising edges of K and K# for each of the two rising edges comprising the WRITE
cycle. See
Pin Arrangement
for signal to data relationships.
x18 device uses BW0#, BW1#.
x36 device uses BW0# to BW3#.
See
Byte Write Operation
for relation between BWx# and Dxx.
Input Clock: This input clock pair registers address and control inputs on the rising edge of
K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times around
the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output data.
The rising edge of C# is used as the output timing reference for first output data. The rising
edge of C is used as the output reference for second output data. Ideally, #C is 180 degrees
out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed
C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH
(i.e. toggle of C and C#)
D0 to Dxx
Input
Q0 to Qxx
Output
LD#
Input
R, W#
Input
BWx#
Input
K, K#
Input
C, C#
Input
R10DS0037EJ0200 Rev.2.00
September 12, 2011
Page 5 of 34
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