FM25040 FRAM
®
Serial Memory
Product Specification
Features
4Kbit Nonvolatile Ferroelectric RAM Organized as 512 x 8
Low Power CMOS Technology
- 10µA Standby Over Industrial Temperature Range
- 5µA Standby Over Commercial Temperature Range
s
Reliable Thin Film Ferroelectric Technology
- 10 Billion (10
10
) Cycle Read/Write Endurance
- 10 Year Data Retention
s
High Performance
- No Write Delay
- Unlimited Sequential Write
s
s
Simple Three Wire Bus
- SPI Compatible (CPOL = 0, CPHA = 0)
- 2.1MHz Maximum Clock Rate
s
Multiple Levels of Write Protection
- Hardware Write Protect Pin
- Internal Write Enable Latch
- Block Protect Bits
- Low Voltage Lockout
s
ESD Protection — Greater Than 2,000V On All Pins
s
True 5V Only Operation
s
8-Pin Mini DIP and SOIC Packages
s
-40° to +85°C Operating Range
s
Description
Ramtron’s FM25040 ferroelectric random access memory, or
FRAM
®
memory provides nonvolatile data integrity in a compact
package. A three wire serial interface provides access to any byte
within the memory while reducing the cost of the processor interface
(as compared to parallel access memories). The FM25040 is useful
in a wide variety of applications for the storage of configuration
information, user programmable data/features, and calibration data.
With Ramtron’s ferroelectric technology, all writes are
nonvolatile, eliminating long delays, extra page mode control, or high
voltage pins. The technology is designed for highly reliable operation,
offering extended endurance and 10 year data retention.
The FM25040 uses the industry standard three wire SPI protocol
for serial chip communication. It is available in 300 mil mini-DIP and
150 mil SOP packages.
Functional Diagram
V
CC
V
SS
Pin Configurations
CS
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
SOP
Power
Detect
Sense Amps
Row Decode
WP
CS
HOLD
SCK
Instruction Decode
Clock Generator
Control Logic
Write Protect
FRAM
Array
Pin Names
Pin Names
Function
Chip Select
Serial Data Out
Write Protect
Ground
Serial Data In
Serial Clock
Hold Input
Supply Voltage
CS
SO
SI
1
Instruction Register
Address Register Counter
11
3
Column Decode
WP
V
SS
Data In/Out Register
3
SI
SO
SCK
HOLD
V
CC
Nonvolatile Status Register
Ramtron reserves the right to change or discontinue this product without notice.
©
1994 Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
Telephone
(800) 545-FRAM, (719) 481-7000
Fax
(719) 488-9095
R2 June 1994
Absolute Maximum Ratings
Description
Ambient Storage or Operating Temperature to
Guarantee Nonvolatility of Stored Data
Voltage on Any Pin with Respect to Ground
D.C. Output Current
Lead Temperature (Soldering, 10 Seconds)
Ratings
-40°C to +85°C
-1.0 to +7.0V
5mA
300°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage
to the device. This is a stress rating only, and the functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%, Unless Otherwise Specified
DC Operating Conditions
Symbol
V
CC
I
CC
I
CC
I
SB
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OH
V
HYS(2)
Parameter
Power Supply Voltage
V
CC
Supply Current
V
CC
Supply Current
Standby Current 0 to 70°C
Standby Current -40 to 85°C
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Hysteresis
Min
4.5
Typ
(1)
Max
5.5
1.5
700
5
10
10
10
Units
V
mA
µA
µA
µA
µA
µA
V
V
V
V
V
I
OL
= 2mA
I
OH
= -1mA
Test Conditions
5.0
1.0
500
1
1
SCK @ 2.1MHz, Read or Write
SCK CMOS Levels, All Other Inputs = V
SS
or V
CC
- 0.3V
SCK @ 1.0MHz, Read or Write
SCK CMOS Levels, All Other Inputs = V
SS
or V
CC
- 0.3V
SCK = SI = V
CC
, All Other Inputs = V
SS
or V
CC
SCK = SI = V
CC
, All Other Inputs = V
SS
or V
CC
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
-1.0
V
CC
x 0.7
V
CC
x 0.3
V
CC
+ 0.5
0.4
V
CC
- .8
V
CC
x .05
(1) Typical values at 25°C, 5.0V.
(2) This paramter is periodically sampled and not 100% tested.
Power-Up Timing
(3)
Symbol
Parameter
Power Up to Read Operation
Power Up to Write Operation
Endurance and Data Retention
Parameter
Endurance
Data Retention
Max
1
1
Units
µs
µs
Min
10 Billion
10
Max
Units
R/W Cycles
Years
t
PUR (2)
t
PUW (2)
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified oper-
ation can be initiated. These parameters are periodically sampled and not 100% tested.
AC Conditions of Test
AC Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Test
V
CC
x 0.1 to V x 0.9
CC
10ns
V
CC
x 0.5
Equivalent AC
Load Circuit
Output
5.0V
2.16K
200pF
3.07K
Capacitance
Symbol
C
OUT(2)
C
IN(2)
Output Capacitance
Input Capacitance
T
A
= 25°C, f = 1.0MHz, V
CC
= 5V
Test
Max
8
6
Units
pF
pF
V
I/O
= 0V
V
IN
= 0V
Conditions
(2) This paramter is periodically sampled and not 100% tested.
2
Pin Descriptions
Hold (/HOLD)
/HOLD may be used to pause the sequence if the CPU must
Serial Output (SO)
process some other event in the middle of an operation. While /HOLD
This pin is active only during a read operation. The pin is high
is low, the FM25040 will ignore any transitions on the SCK and /CS
impedance at all other times and when /HOLD is low. During a read
pins. When /HOLD is high, all operations will proceed normally.
operation, this line is driven high or low depending on the current
Transitions on the /HOLD pin must occur while SCK is low.
data output bit. Data is clocked out of the FM25040 on the falling
edge of the serial clock.
Device Operation
Serial Input (SI)
Data is clocked into the FM25040 via this pin on the rising
edge of the serial clock signal. Beyond the setup and hold times
around this clock edge, the state on this pin is ignored. However,
this pin should be driven to a valid logic level at all times to prevent
excessive power dissipation.
The FM25040 is a serial ferroelectric memory designed to
interface easily with the Serial Peripheral Interface (SPI) port
common to many MC6805 and MC68HC11 processors. The SPI
communications channel uses three wires (clock, serial data in,
and serial data out) that can be shared among a number of devices.
Additionally, a fourth pin (chip select) selects the device on the
time multiplexed bus that should respond to the access request. A
Serial Clock (SCK)
typical system configuration is shown in Figure 1.
Information is clocked into or out of the FM25040 using this
Data is transferred to and from the FM25040 in bytes of eight
pin when /CS is low and /HOLD is high. Input values are latched on
bits each, governed by edges on the SCK signal. Data is transferred
the rising edge, while data output changes occur after the falling
with the most significant bit (MSB) first. For any operation the first
edge of this signal. The maximum clock rate is 2.1MHz. The FM25040
byte to be transferred is the operation code (opcode) which
is a completely static design, so clocking may be interrupted at any
determines what is to be performed by the memory. There are six
point in time, or the clock rate may be arbitrarily slow.
operations that may be performed by the FM25040. Table 1 lists the
operation with its corresponding opcode.
Chip Select (/CS)
When this signal is low, the FM25040 will respond to
Table 1. Opcode Commands
transitions on the SCK signal. When it is high, inputs are ignored,
outputs are placed in a high impedance state, and the FM25040
Opcode
Description
Name
goes into its low power standby mode. A high to low transition is
0000 0110
Set Write Enable Latch
WREN
required on this pin before each opcode.
Write Protect (/WP)
If held low, this pin will inhibit all write operations within the
part, regardless of the state of the internal write enable latch. If
held high, writes are permitted only if the internal write enable
latch is set. Read operations always proceed normally, regardless of
the state of this pin.
0000 0100
0000 0101
0000 0001
0000 A011
0000 A010
Write Disable
Read Status Register
Write Status Register
Read Data
Write Data
WRDI
RDSR
WRSR
READ
WRITE
Figure 1. Typical System Configuration
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
Bus
Master
SS
1
SS
2
HOLD
1
HOLD
2
Master Acronym Definitions
MOSI: Master Out Slave In
MISO: Master In Slave Out
SS: Slave Select
Slave 1
FM25040
CS
HOLD
Slave 2
FM25040
CS
HOLD
3
Status Register
Table 2 shows the organization of the status register. The
register is read using the RDSR instruction. Bits 0 and 4 through 7
are unused. When read, they return a 0. The value of the status
register is transmitted directly after the RDSR opcode. Executing of
the RDSR instruction has no effect on the status register bits. (This
is unlike the WRSR instruction which clears the Write Enable Latch
[WEL] bit.)
Bit 1 is the WEL. When set, writes may take place to the part.
When reset, all writes will be ignored.
Bits 2 and 3 are nonvolatile block protect bits (BP0 and BP1).
These bits provide further protection to portions of the array as
specified in Table 3. Note that bytes within blocks that are
not
protected with BP0 and BP1 will still only be written if the write
enable latch is set.
Writing to the status register is a two step process:
i) The WEL bit must be set to enable a write. This is done
using the WREN instruction.
ii) The WRSR instruction is then used to change the block
protect bits. Note that execution of the WRSR instruction
clears the WEL bit.
Table 2. Status Register Organization
Bit
Name
7
0
6
0
5
0
4
0
3
BP1
2
BP0
1
WEL
0
0
Write Enable Latch
The internal write enable latch on the FM25040 prevents
writes to the data within the part while it is cleared. /WEL = 0
protects the nonvolatile memory array
and
the status register bits.
When set to a 1, writes proceed normally. It is automatically
cleared on power up or whenever the power supply falls below
3.5V (typical). It is also cleared after all write operations
(including WRSR) and cleared whenever /WP is brought low. Note
that /WP going low asynchronously clears the WEL bit regardless of
the status of the /HOLD pin.
The user can set or reset this bit by transmitting the
corresponding opcode to the FM25040 (WREN or WRDI,
respectively). No address or data bytes follow the opcode. Note that
following the write enable latch instruction (WREN), chip select
must rise again before a write sequence may be started. The
FM25040 will ignore all bits transmitted after the opcode but
before the rise of /CS.
Read and Write Sequences
For a read or write operation, an address byte must be
transmitted to the FM25040 after the opcode. Bit 3 of the opcode is
address bit A
8
. Following the address byte, data bytes should be
transferred MSB first. Any number of bytes may be read or written
in sequential order starting with the specified address, and
wrapping around to address 0 after the byte at address 1FF (hex) is
accessed. The read or write sequence continues until /CS is
brought high.
Note that on the FRAM device, any number of bytes may be
written with a single write sequence, while EEPROM based 25040
devices are limited to one through four bytes only. To
accommodate this feature, the actual write to the nonvolatile array
takes place after the eighth bit in each byte is transmitted. If /CS
rises during a write operation, only the byte that has not been
completely transmitted will be ignored.
Low Voltage Protection
When powering up, the FM25040 will automatically perform
an internal reset and await a high to low transition on /CS from the
bus master. The bus master should wait T
PUR
(or T
PUW
) after V
CC
reaches 4.5V before selecting the part. Additionally, whenever V
CC
falls below 3.5V (typical), the part goes into its low voltage
protection mode. In this mode, all accesses to the part are
inhibited and the part performs an internal reset. If an access was
in progress when the power supply fails, it will be automatically
aborted by the FM25040.
Table 3. Memory Block Protect Bits
BP1
0
0
1
1
BP0
0
1
0
1
None
Protected Address Range (Hex)
180
→
1FF (upper 1/4 of the array)
100
→
1FF (upper 1/2 of the array)
000
→
1FF (all of the array)
4
Serial Data Output Timing
Serial output timing is shown in Figure 2. Data is placed by the
FM25040 on it serial output pin (SO) t
ODV
seconds after the falling
edge of SCK. The clock frequency is arbitrary with a maximum
clock rate of 2.1MHz. This is the timing sequence that applies to
the reading of the status register bits and nonvolatile memory.
Serial Data Output Timing Parameters
(4,5)
Symbol
f
CK
t
CH
t
CL
t
CSL
t
OD
t
ODV
t
OH
Parameter
Clock Frequency
Clock High Time
Clock Low Time
Chip Select Lag Time
Output Disable Time
Output Data Valid Time
Output Hold Time
Min
0
190
190
240
Max
2.1
Units
MHz
ns
ns
ns
240
240
0
ns
ns
ns
(4) T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%, Unless Otherwise Specified
(5) Switching Times Measured from 50% VCC to 50% VCC, Unless Otherwise Specified
Figure 2. Serial Data Output Timing Diagram
CS
t
CSL
t
CL
t
CH
SCK
t
ODV
t
OH
MSB
Bits 6 - 1
LSB
t
OD
High Z
SO
High Z
Serial Data Input Timing
Serial input timing is shown in Figure 3. Input data is latched
on the rising edge of SCL. The data bit must be valid t
SU
seconds
before this rising edge. In addition, data must be held t
HLD
seconds
after this rising edge. This is the timing sequence that applies to the
clocking of all opcodes, addresses, and data to be written to the
status register and memory.
Serial Data Input Timing Parameters
(4)
Symbol
t
D
t
F(6)
t
HLD
t
LE
t
R(6)
t
SU
Parameter
Deselect Time
Data Fall Time
Data Hold Time
Chip Select Lead Time
Data Rise Time
Data Setup Time
Min
240
Max
Units
ns
2.0
100
240
2.0
100
µs
ns
ns
µs
ns
(4) T
A
= -40°C to +85°C, V
CC
= 5.0V ±10%, Unless Otherwise Specified
(6) Rise and Fall Times Measured Between 10% and 90% Points of Waveform
Figure 3. Serial Data Input Timing Diagram
CS
t
LE
t
R
t
f
t
D
t
CSL
SCK
t
SU
t
HLD
MSB
Bits 6-1
LSB
SI
5
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