A d van ced v.1
54SXA Family FPGAs
Specifications
Output Tristate at Powerup
• 100% Resource Utilization with 100% Pin Locking
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with
5.0V Input Tolerance
• Very Low Power Consumption
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug capability
with Silicon Explorer
• JTAG Boundary Scan Testing in Compliance with
IEEE Standard 1149.1
• Actel Designer Series Design Tools, Supported by
Cadence, Exemplar, IST, Mentor Graphics, Model
Tech, Synopsys, Synplicity, and Viewlogic Design
Entry and Simulation Tools
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• 8,000 to 72,000 Available Logic Gates
• Up to 360 User-Programmable I/O Pins
• 4,024 Flip-Flops
• 0.25 Micro CMOS
Features
• I/Os with Live, or “Hot,” Insertion/Removal Capability
• Power Up/Down Friendly (No Sequencing Required
for Supply Voltage)
• 66 MHz PCI
• CPLD and FPGA Integration
• Single Chip Solution
• Configurable I/Os to Support Varity of I/O Standards,
Such as 3.3V PCI, LVTTL, TTL, and 5V PCI.
• Configurable Weak Resistor Pullup or Pulldown for
SX Pr odu ct Prof ile
A54SX08A
Gate Capacity
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum Flip-Flops
User I/Os (Maximum)
Clocks
Quadrant Clocks
JTAG
PCI
Clock-to-Out
Input Set-Up (External)
Speed Grades
Temperature Grades
Packages (by pin count)
PQFP
TQFP
PBGA
8,000
768
512
256
512
130
3
0
Yes
Yes
TBD
TBD
Std, –1, –2, –3
C, I, M
208
100, 144
144
A54SX16A
16,000
1,452
924
528
990
177
3
0
Yes
Yes
TBD
TBD
Std, –1, –2, –3
C, I, M
208
100, 144
144
A54SX32A
32,000
2,880
1,800
1,080
1,980
249
3
0
Yes
Yes
4.5 ns
-1.3 ns
Std, –1, –2, –3
C, I, M
208
144
144, 256, 329
A54SX72A
72,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
4.8 ns
-3.3 ns
Std, –1, –2, –3
C, I, M
208
—
484
Apr il 1 9 9 9
1
© 1999 Actel Corporation
G eneral D es crip t ion
The New SXA Family of FPGAs
Actel’s SXA Family of FPGAs features a revolutionary
new
sea-of-modules
architecture
that
delivers
next-generation device performance and integration levels
not currently achieved by any other FPGA architecture.
SXA devices greatly simplify design time, enable dramatic
reductions in design costs and power consumption, and
further speed time-to-market for performance-intensive
applications.
Fast and Flexible New Architecture
Actel’s SXA architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient mapping
of synthesized logic functions. Optimal use of the silicon is
made by locating the routing and interconnect resources in
the metal layers above the logic modules. This enables the
entire floor of the device to be spanned with an
uninterrupted grid of fine-grained, synthesis-friendly logic
modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules.
To minimize signal propagation delay, SXA devices
employ both local and general routing resources. The
high-speed local routing resources (DirectConnect and
O rdering In forma t ion
A54SX16
A
–
2
PQ
208
FastConnect) enable very fast local signal propagation that
is optimal for fast counters, state machines, and datapath
logic. The general system of segmented routing tracks
allows any logic module in the array to be connected to
any other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number of
antifuse interconnect elements to five (typically 90% of
connections use only three antifuses). The unique local and
general routing structure featured in SXA devices gives
fast and predictable performance, allows 100%
pin-locking with full logic utilization, enables concurrent
PCB development, reduces design time, and allows
designers to achieve performance goals with a minimum of
effort.
Further complementing the SXA’s flexible routing
structure is a hard-wired, constantly-loaded clock network
that has been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast
clock-to-out or fast input set-up times. SXA devices have
easy-to-use I/O cells which do not require HDL
instantiation, facilitating design re-use and reducing design
and debugging time.
Application (Temperature Range)
Blank = Commercial (0 to +70 C)
I = Industrial (–40 to +85 C)
M = Military (–55 to +125 C)
PP = Pre-production
Package Lead Count
Package Type
BG = 1.27mm Ball Grid Array
fBG = 1.0 mm Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
A =
0.25
Micro CMOS Technology
Part Number
A54SX08A
A54SX16A
A54SX32A
A54SX72A
=
=
=
=
8,000 Gates
16,000 Gates
32,000 Gates
72,000 Gates
2
54 SXA F am i ly F PG As
Prod uc t Pla n
Speed Grade*
Std
A54SX08A Device
100-Pin Thin Quad Flat Pack (TQFP)
144-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
144-Pin Plastic Ball Grid Array (fBGA)
A54SX16A Device
100-Pin Thin Quad Flat Pack (TQFP)
144-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
144-Pin Plastic Ball Grid Array (fBGA)
256-Pin Plastic Ball Grid Array (fBGA)
A54SX32A Device
144-Pin Thin Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
144-Pin Plastic Ball Grid Array (fBGA)
256-Pin Plastic Ball Grid Array (fBGA)
329-Pin Plastic Ball Grid Array (BGA)
A54SX72A Device
208-Pin Plastic Quad Flat Pack (PQFP)
484-Pin Plastic Ball Grid Array (fBGA)
Consult your local Actel sales representative for product availability.
Applications: C = Commercial
Availability:
= Available
I = Industrial
P = Planned
M = Military
— = Not Planned
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
–1
–2
–3
C
Application
I
†
M
•
*Speed Grade: –1 = Approx. 15% Faster than Standard
–2 = Approx. 25% Faster than Standard
–3 = Approx. 35% Faster than Standard
† Only Std, –1, –2 Speed Grade
• Only Std, –1 Speed Grade
Plas t ic D ev ice Res o u r ce s
User I/Os (including clock buffers)
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
PQFP
208-Pin
130
175
174
173
TQFP
100-Pin
81
81
—
—
TQFP
144-Pin
113
113
113
—
fBGA
144-Pin
TBD
TBD
TBD
—
fBGA
256-Pin
—
—
TBD
—
BGA
329-Pin
—
—
249
—
fBGA
484-Pin
—
—
—
360
Package Definitions
(Consult your local Actel sales representative for product availability.)
PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = 1.27mm Plastic Ball Grid Array, fBGA = 1.0mm Plastic
Ball Grid Array.
3
Pin Descript ion
CLKA/B
Clock A and B
TTL/3.3V PCI clock input for clock distribution networks.
The clock input is buffered prior to clocking the R-cells. If
not used, this pin must be set LOW or HIGH on the board.
It must not be left floating.
QCLKA/B/C/D
Quadrant Clock A, B, C, and D
until the internal JTAG state machine reaches the “logic
reset” state. At this point the JTAG pins will be released
and will function as regular I/O pins. The “logic reset”
state is reached 5 TCK cycles after the TMS pin is set
HIGH. In dedicated JTAG mode, TMS functions as
specified in the IEEE 499.1 JTAG Specifications. JTAG
operation is further described on page 10.
NC
No Connection
These four pins are the quadrant clock inputs. They are
TTL/3.3V PCI clock input for clock distribution networks.
Each of these clock inputs can drive up to a quarter of the
chip, and they can be grouped together to drive multiple
quadrants. The clock input is buffered prior to clocking the
R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating. (These quadrant
clocks are only for 54SX72A).
TCK
Test Clock
This pin is not connected to circuitry within the device.
PRA
Probe A
The Probe A pin is used to output data from any
user-defined design node within the device. This
independent diagnostic pin can be used in conjunction with
the Probe B pin to allow real-time diagnostic output of any
signal path within the device. The Probe A pin can be used
as a user-defined I/O when debugging has been completed.
PRB
Probe B
Test clock input for diagnostic probe and device
programming. In flexible mode (refer to the JTAG pins
functionality table), TCK becomes active when the TMS
pin is set LOW. This pin functions as an I/O when the
JTAG state machine reaches the “logic reset” state.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired) Array Clock
The Probe B pin is used to output data from any node
within the device. This diagnostic pin can be used in
conjunction with the Probe A pin to allow real-time
diagnostic output of any signal path within the device. The
Probe B pin can be used as a user-defined I/O when
debugging has been completed.
TDI
Test Data Input
TTL clock input for sequential modules. This input is
directly wired to each R-cell and offers clock speeds
independent of the number of R-cells being driven. If not
used, this pin must be set LOW or HIGH on the board. It
must not be left floating.
I/O
Input/Output
Serial input for JTAG and diagnostic probe. In flexible
mode, (refer to the JTAG pins functionality table), TDI is
active when the TMS pin is set LOW. This pin functions as
an I/O when the JTAG state machine reaches the “logic
reset” state.
TDO
Test Data Output
The I/O pin functions as an input, output, three-state, or
bi-directional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications.
Unused I/O pins are tri-stated by the Designer Series
software.
TMS
Test Mode Select
Serial output for JTAG. In flexible mode (Refer to the
JTAG pins functionality table), TDO is active when the
TMS pin is set LOW. This pin functions as an I/O when
the JTAG state machine reaches the “logic reset” state.
V
CCI
Supply Voltage
Supply voltage for I/Os.
V
CCA
Supply Voltage
The TMS pin controls the use of JTAG pins (TCK, TDI,
TDO). In flexible mode (refer to the JTAG pins
functionality table), when the TMS pin is set LOW, the
TCK, TDI, and TDO pins are JTAG pins. Once the JTAG
pins are in JTAG mode they will remain in JTAG mode
Table 1 •
Supply Voltages
V
CCA
A54SX08A
A54SX16A
A54SX32A
A54SX72A
2.5V
2.5V
2.5V
V
CCI
2.5V
3.3V
5.0V
Supply voltage for Array.
Maximum Input
Tolerance
5.0V
5.0V
5.0V
Maximum Output
Drive
2.5V
3.3V
5.0V
4
54 SXA F am i ly F PG As
SXA Fa mily Ar chitec tu r e
The SXA Family architecture was designed to satisfy
next-generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are normally
open circuit and, when programmed, form a permanent
low-impedance connection.
The extremely small size of these interconnect elements
gives the SXA Family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and unprogrammed antifuses, and there is no
configuration bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and metal
tracks) have lower capacitance and lower resistance than
any other device of similar capacity, leading to the fastest
signal propagation in the industry.
Actel’s new SXA Family provides much more efficient
use of silicon by locating the routing interconnect
resources between the Metal 2 (M2) and Metal 3 (M3)
layers (see Figure 1). This completely eliminates the
channels of routing and interconnect resources between
logic modules (as implemented on SRAM FPGAs and
previous generations of antifuse FPGAs), and enables the
entire floor of the device to be spanned with an
uninterrupted grid of logic modules.
Routing Tracks
Metal 3
Amorphous Silicon/
Dielectric Antifuse
Tungsten Plug Via
Tungsten Plug Via
Metal 2
Metal 1
Tungsten Plug
Contact
Silicon Substrate
Figure 1 •
SXA Family Interconnect Elements
5
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