eight-pin version and accepts one reference input and
drives out one low-skew clock.
All parts have on-chip PLLs that lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad, internal to the device.
Multiple ASM3P622S01B/J devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
The output has less than 200pS of cycle-to-cycle jitter. The
input and output propagation delay is guaranteed to be less
than 250pS, and the output-to-output skew is guaranteed to
be less than 250pS.
Less than 200pS cycle-to-cycle jitter
Available in 8pin, 150 mil SOIC, 4.4mm TSSOP
Package
3.3V Operation
Industrial temperature range
Advanced CMOS technology
The First True Drop-in Solution
Functional Description
ASM3P622S01B/J is a versatile, 3.3V Zero-delay buffer
designed to distribute low frequency Timing-Safe™ clocks
with Peak EMI Reduction. The ASM3P622S01B/J is the
Refer
“
Spread Spectrum Control and Input-Output Skew
Table”
for
deviations
and
Input-Output
Skew for
ASM3P622S01B/J devices.
Block Diagram
V
DD
SSON
SS%
Modulation
XIN/CLKIN
XOUT
Crystal
Oscillator
Reference
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Feedforward
Divider
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2007
rev 0.4
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P622S01B/J
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating the clock frequency. The ASM3P622S01B/J
uses the center modulation spread spectrum technique in
which the modulated output frequency varies above and
below
the
reference
frequency
with
a
specified
modulation rate. With center modulation, the average
frequency is the same as the unmodulated frequency and
there is no performance degradation.
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Pin Configuration
CLKIN
CLKOUT1
SS%
1
2
8
7
CLKOUT3
V
DD
CLKOUT2
SSON
ASM3P622S01B
3
6
5
GND
4
XIN / CLKIN
XOUT
SS%
1
2
8
7
CLKOUT2
V
DD
CLKOUT1
SSON
ASM3P622S01J
3
6
5
GND
4
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 12
May 2007
rev 0.4
Pin Description for ASM3P622S01B
Pin #
1
2
3
4
5
6
7
8
ASM3P622S01B/J
Pin Name
CLKIN
CLKOUT1
1
SS%
2
GND
SSON
2
CLKOUT2
1
V
DD
CLKOUT3
1
Buffered clock output
Spread Spectrum Selection
Ground
Description
Input reference frequency, 5V-tolerant input
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
Buffered clock output
Notes: 1. Weak pull-down on all outputs.
2. Weak pull-up on these Inputs.
3. Buffered clock outputs are Timing-Safe™
Pin Description for ASM3P622S01J
Pin #
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
SS%
2
GND
SSON
2
CLKOUT
1
V
DD
CLKOUT
1
Description
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Spread Spectrum Selection
Ground
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
Buffered clock output
Notes: 1. Weak pull-down on all outputs
2. Weak pull-up on these Inputs
3. Buffered clock outputs are Timing-Safe™
Spread Spectrum Control and Input-Output Skew Table
Device
ASM3P622S01B/J
Input Frequency
12MHz
SS %
0
1
Deviation
±0.25 %
±0.50 %
Input-Output Skew(±T
SKEW
)
0.063
0.125
Note: T
SKEW
is measured in units of the Clock Period
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 12
May 2007
rev 0.4
Absolute Maximum Ratings
Symbol
VDD
T
STG
T
s
T
J
T
DV
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
ASM3P622S01B/J
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
260
150
2
Unit
V
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions for ASM3P622S01B/J Device
Parameter
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
-40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Electrical Characteristics for ASM3P622S01B/J
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
Description
Input LOW Voltage
1
Input HIGH Voltage
1
Input LOW Current
Input HIGH Current
Output LOW Voltage
2
Output HIGH Voltage
2
Supply Current
Output Impedance
V
IN
= 0V
Test Conditions
Min
2.0
Typ
Max
0.8
50
100
0.4
Unit
V
V
µA
µA
V
V
mA
Ω
V
IN
= V
DD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
Note: 1. CLKIN input has a threshold voltage of VDD/2
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 12
May 2007
rev 0.4
Switching Characteristics for ASM3P622S01B/J
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
ASM3P622S01B/J
Description
Output Frequency
Duty Cycle
2
= (t
2
/ t
1
) * 100
Output Rise Time
1, 2
Output Fall Time
1, 2
Output-to-output skew
2
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
2
Test Conditions
30pF load
Measured at V
DD
/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
4
40
Typ
50
Max
20
60
2.5
2.5
250
±250
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Device-to-Device Skew
2
Cycle-to-cycle jitter
2
PLL Lock Time
2
Note: 1. The parameters specified with loaded outputs.
2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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