available in 8pin package. The ASM3P623S01J is the
eight-pin version with crystal interface and accepts one
reference input and drives out two low-skew clocks.
All parts have on-chip PLLs that lock to an input clock on
the CLKIN pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad, internal to the device.
Multiple ASM3P623S01B/C/J devices can accept the same
input clock and distribute it. In this case, the skew between
the outputs of the two devices is guaranteed to be less than
700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 250pS, and the output-to-output skew is
guaranteed to be less than 250pS.
Less than 200pS cycle-to-cycle jitter
Available in 8pin, 150 mil SOIC, 4.4mm TSSOP
Packages (ASM3P623S00B/C/J)
3.3V operation
Industrial temperature range
Advanced 0.35µ CMOS technology
The First True Drop-in Solution
Functional Description
ASM3P623S01B/C/J is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed Timing-Safe™ clocks
with Peak EMI reduction. ASM3P623S01B/C accepts one
reference input and drives out three low-skew clocks. It is
Refer
“
Spread Spectrum Control and Input-Output Skew
Table”
for
deviations
and
Input-Output
Skew for
ASM3P623S01B/C/J devices
Block Diagram
VDD
SSON
SS%
Modulation
XIN/CLKIN
XOUT
Crystal
Oscillator
Reference
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
VCO
PLL
Feedforward
Divider
CLKOUT
GND
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2007
rev 0.4
Spread Spectrum Frequency Generation
The clocks in digital systems are typically square waves
with a 50% duty cycle and as frequencies increase the
edge rates also get faster. Analysis shows that a square
wave is composed of fundamental frequency and
harmonics. The fundamental frequency and harmonics
generate the energy peaks that become the source of
EMI. Regulatory agencies test electronic equipment by
measuring the amount of peak energy radiated from the
equipment. In fact, the peak level allowed decreases as
the frequency increases. The standard methods of
reducing EMI are to use shielding, filtering, multi-layer
ASM3P623S01B/C/J
PCBs etc. These methods are expensive. Spread
spectrum clocking reduces the peak energy by reducing
the Q factor of the clock. This is done by slowly
modulating
the
clock
frequency.
The
ASM3P623S01B/C/J uses the center modulation spread
spectrum technique in which the modulated output
frequency varies above and below the reference
frequency with a specified modulation rate. With center
modulation, the average frequency is the same as the
unmodulated frequency and there is no performance
degradation
Timing-Safe™ technology
Timing-Safe™ technology is the ability to modulate a
clock source with Spread Spectrum technology and
maintain synchronization with any associated data path.
Pin Configuration
CLKIN
1
8
7
6
5
CLKOUT
VDD
CLKOUT2
SSON
CLKOUT1
2
SS%
3
GND
4
ASM3P623S01B/C
XIN/CLKIN
1
8
7
6
5
CLKOUT
VDD
CLKOUT1
SSON
XOUT
2
SS%
3
GND
4
ASM3P623S01J
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 12
May 2007
rev 0.4
Pin Description for ASM3P623S01B/C
Pin #
1
2
3
4
5
6
7
8
ASM3P623S01B/C/J
Pin Name
CLKIN
CLKOUT
2
SS%
3
GND
SSON
3
CLKOUT
2
VDD
CLKOUT
1,2
Buffered clock output
Spread Spectrum Selection
Ground
Description
Input reference frequency, 5V-tolerant input
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
Buffered clock output
Notes:
1. This output is driven and has an internal feedback for the PLL.
2. Weak pull-down on all outputs. 3. Weak pull-up on these inputs
4. Buffered clock outputs are Timing-Safe™
Pin Description for ASM3P623S01J
Pin #
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
SS%
2
GND
SSON
2
CLKOUT
1
VDD
CLKOUT
1,3
Description
Crystal connection or external reference frequency input. This pin has dual functions. It
can be connected either to an external crystal or an external reference clock.
Crystal connection. If using an external reference, this pin must be left unconnected.
Spread Spectrum Selection
Ground
Spread Spectrum enable and disable option When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum.
Buffered clock output
3.3V supply
Buffered clock output
Notes:
1. Weak pull-down on all outputs. 2. Weak pull-up on these inputs
3. This output is driven and has an internal feedback for the PLL.
4. Buffered clock outputs are Timing-Safe™
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 12
May 2007
rev 0.4
Spread Spectrum Control and Input-Output Skew Table
(Note: The values given in the table are for an input frequency of 32 MHz)
ASM3P623S01B/C/J
Device
ASM3P623S01B
SS%
0
1
0
1
0
1
Deviation
±0.25 %
±0.5 %
±.125 %
±0.25 %
±0.125 %
±0.25 %
Input-Output Skew(±T
SKEW
)
0.125
0.25
0.125
0.25
0.125
0.25
ASM3P623S01C
ASM3P623S01J
Note: T
SKEW
is measured in units of the Clock Period
Absolute Maximum Rating
Symbol
VDD
T
STG
T
s
T
J
T
DV
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
260
150
2
Unit
V
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Operating Conditions for ASM3P623S01B/C/J Devices
Parameter
VDD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
Description
Min
3.0
-40
Max
3.6
+85
30
7
Unit
V
°C
pF
pF
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 12
May 2007
rev 0.4
Electrical Characteristics for ASM3P623S01B/C/J
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Z
o
ASM3P623S01B/C/J
Description
Input LOW Voltage
5
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
6
Output HIGH Voltage
6
Supply Current
Output Impedance
5
Test Conditions
Min
2.0
Typ
Max
0.8
Unit
V
V
µA
µA
V
V
mA
Ω
V
IN
= 0V
V
IN
= VDD
I
OL
= 8mA
I
OH
= -8mA
Unloaded outputs
2.4
15
23
50
100
0.4
Switching Characteristics for ASM3P623S01B/C/J
7
Parameter
1/t
1
t
3
t
4
t
5
t
6
t
7
t
J
t
LOCK
Description
Output Frequency
Duty Cycle
6
= (t
2
/ t
1
) * 100
Output Rise Time
Output Fall Time
6
Output-to-output skew
CLKOUT Rising Edge
6
6
Test Conditions
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded
Measured at VDD /2
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
Stable power supply, valid clock presented
on CLKIN pin
Min
20
40
Typ
50
Max
50
60
2.5
2.5
250
±350
700
200
1.0
Unit
MHz
%
nS
nS
pS
pS
pS
pS
mS
Delay, CLKIN Rising Edge to
6
Device-to-Device Skew
6
Cycle-to-cycle jitter
6
PLL Lock Time
6
Notes:
5. CLKIN input has a threshold voltage of VDD/2
6. Parameter is guaranteed by design and characterization. Not 100% tested in production
7. All parameters specified with loaded outputs.
Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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