High-Performance 1:10 Clock Driver for General Purpose
applications. Operates up to 200 MHz at 3.3V Supply
Voltage
•
Pin-to-Pin Skew < 100 pS at 3.3V Supply Voltage
•
Supply Range : 2.3V to 3.6V
•
Operating Temperature Range : -40°C to 85°C
•
Output Enable Glitch Suppression
•
Distributes One Clock Input to Two Banks of Five
Outputs
•
25Ω On Chip Series Damping Resistors
•
Packaged in 24 Pin TSSOP Package
ASM2P2310A
Product Description
The ASM2P2310A is a high-performance, low-skew clock
buffer that operates up to 200MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power
up, the default state of the outputs is low regardless of the
state of the control pins. For normal operation, the outputs
of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state
when the control pins (1G or 2G, respectively) are held low
and a negative clock edge is detected on the CLK input.
The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into
the buffer mode when the control pins (1G and 2G) are
held high and a negative clock edge is detected on the CLK
input. The device operates in a 2.5V and 3.3V environment.
The built-in output enable glitch suppression ensures a
synchronized output enable sequence to distribute full
period clock signals.
The ASM2P2310A is characterized for operation from
-40°C to 85°C.
Block Diagram
CLK
24
3
25Ω
1Y0
21
25Ω
2Y0
4
25Ω
1Y1
20
25Ω
2Y1
5
25Ω
1Y2
17
25Ω
2Y2
8
25Ω
1Y3
16
25Ω
2Y3
9
1G
11
25Ω
LOGIC CONTROL
1Y4
2G
13
LOGIC CONTROL
12
25Ω
2Y4
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2005
rev 0.2
Pin Configuration
GND
V
DD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
DD
1G
2Y4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CLK
V
DD
V
DD
2Y0
2Y1
GND
GND
2Y2
2Y3
V
DD
V
DD
2G
ASM2P2310A
ASM2P2310A
19
18
17
16
15
14
13
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
GND
V
DD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
DD
1G
2Y4
2G
V
DD
V
DD
2Y3
2Y2
GND
GND
2Y1
2Y0
V
DD
V
DD
CLK
Type
P
P
O
O
O
P
P
O
O
P
I
O
I
P
P
O
O
P
P
O
O
P
P
I
Ground Pin
DC Power supply, 2.3 V – 3.6V
Buffered Output Clock
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
Description
DC power supply, 2.3V – 3.6V
Output enable control for 1Y[0:4] outputs.
meaning the 1Y[0:4] clock outputs follow the
high.
Buffered Output Clock
Output enable control for 2Y[0:4] outputs.
meaning the 2Y[0:4] clock outputs follow the
high.
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Input reference frequency
This output enable is active-high,
input clock (CLK) if this pin is logic
This output enable is active-high,
input clock (CLK) if this pin is logic
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
2 of 11
October 2005
rev 0.2
Function Table
Input
2G
L
L
H
H
ASM2P2310A
Output
CLK
↓
↓
↓
↓
1G
L
H
L
H
1Y[0:4]
L
CLK
L
CLK
1
1
2Y[0:4]
L
L
CLK
1
CLK
1
Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high.
Detailed Description
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input
such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the
input clock) (see Figure 1).
The G input must fulfill the timing requirements (t
su
, t
h
) according to the Switching Characteristics table for predictable
operation
.
CLK
G
n
Y
n
t
su(en)
t
h(en)
a) Enable Mode
CLK
G
n
Y
n
t
su(dis)
t
h(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
3 of 11
October 2005
rev 0.2
Absolute Maximum Ratings
Parameter
Supply Voltage range, V
DD
Input Voltage range, V
I
1,2
1,2
ASM2P2310A
Rating
-0.5V to 4.6V
-0.5 V to V
DD
+ 0.5 V
-0.5 V to V
DD
+ 0.5 V
±50 mA
120°C/W
-65°C to 150°C
2KV
Output Voltage range, V
O
Continuous total output current, I
O
(V
O
= 0 to V
DD
)
Package thermal impedance,
θ
JA3
: PW package
Storage temperature range T
stg
Static Discharge Voltage , t
DV
(As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Notes :
1 The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2 This value is limited to 4.6 V maximum.
3 The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions
1
Parameter
Supply voltage, V
DD
Low-level input voltage, V
IL
High-level input voltage, V
IH
Input voltage, V
I
High-level output current, I
OH
Low-level output current, I
OL
V
DD
= 3V to 3.6V
V
DD
= 2.3 V to 2.7V
V
DD
= 3V to 3.6V
V
DD
= 2.3V to 2.7V
V
DD
= 3V to 3.6V
V
DD
= 2.3V to 2.7V
V
DD
= 3V to 3.6V
V
DD
= 2.3V to 2.7V
Min
2.3
-
-
-
2
1.7
0
-
-
-
-
–40
Typ
2.5
3.3
-
-
-
-
-
-
-
-
-
-
Max
-
3.6
0.8
0.7
-
-
V
DD
12
6
12
6
85
Unit
V
V
V
V
mA
mA
°C
Operating free-air temperature, T
A
Note:1 Unused inputs must be held high or low to prevent them from floating.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
4 of 11
October 2005
rev 0.2
Electrical Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
ASM2P2310A
Symbol
V
IK
I
I
I
DD2
C
I
C
O
Parameter
Input voltage
Input current
Static device current
Input capacitance
Output capacitance
V
DD
= 3V,
V
I
= 0V or V
DD
Test Conditions
I
I
= -18 mA
I
O
= 0 mA
V
I
= 0V or V
DD
V
I
= 0V or V
DD
Min
-
-
-
-
-
Typ
1
-
-
-
2.5
2.8
Max
-1.2
±5
80
-
-
Unit
V
µA
µA
pF
pF
CLK = 0V or V
DD
,
V
DD
= 2.3V to 3.6V,
V
DD
= 2.3V to 3.6V,
Note: 1 All typical values are at respective nominal V
DD
.
2 For I
CC
over frequency, see Figure 6.
V
DD
= 3.3 V
±
0.3 V
Symbol
V
OH
Parameter
High-level output
voltage
V
DD
= 3 V
Test Conditions
V
DD
= Min to Max,
I
OH
= -100 µA
I
OH
= -12 mA
I
OH
= -6 mA
I
OL
= -100 µA
I
OL
= 12mA
I
OL
= 6 mA
V
O
= 1V
V
O
= 1.65V
V
O
= 3.135V
V
O
= 1.95V
V
O
= 1.65V
V
O
= 0.4V
Min
V
DD
- 0.2
2.1
2.4
-
-
-
-28
-
-
28
Typ
1
-
-
-
-
-
-
-
-36
-
-
36
Max
-
-
-
0.2
0.8
0.55
-
-
-14
-
Unit
V
V
OL
Low-level output
voltage
V
DD
= Min to Max,
V
DD
= 3V
V
DD
= 3V,
V
DD
= 3.3V,
V
DD
= 3.6V,
V
DD
= 3V,
V
DD
= 3.3V,
V
DD
= 3.6V,
V
I
OH
High-level output
current
Low-level output
current
mA
I
OL
-
-
-
14
-
mA
Note: 1 All typical values are at respective nominal V
DD
.
V
DD
= 2.5 V
±0.2
V
Symbol
V
OH
V
OL
Parameter
High-level output voltage
Low-level output voltage
V
DD
= 2.3V
Test Conditions
V
DD
= Min to Max,
V
DD
= Min to Max,
V
DD
= 2.3V
V
DD
= 2.3V,
V
DD
= 2.5V,
V
DD
= 2.7V,
V
DD
= 2.3V,
I
OH
= -100 µA
I
OH
= -6 mA
I
OL
= 100 µA
I
OL
= 6 mA
V
O
= 1V
V
O
= 1.25V
V
O
= 2.375V
V
O
= 1.2V
V
O
= 1.25V
V
O
= 0.3V
Min
V
DD
- 0.2
1.8
-
-
-17
-
-
17
Typ
1
-
-
-
-
-
-25
-
-
25
Max
-
-
0.2
0.55
-
-
-10
-
Unit
V
V
I
OH
High-level output current
mA
I
OL
Low-level output current
V
DD
= 2.5V,
V
DD
= 2.7V,
-
-
-
10
mA
-
Note: 1 All typical values are at respective nominal V
DD
.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
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