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ASM2P2351AHG-24AT

产品描述Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, GREEN, SSOP-24
产品类别逻辑    逻辑   
文件大小479KB,共13页
制造商ALSC [Alliance Semiconductor Corporation]
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ASM2P2351AHG-24AT概述

Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, GREEN, SSOP-24

ASM2P2351AHG-24AT规格参数

参数名称属性值
零件包装代码SSOP
包装说明SSOP,
针数24
Reach Compliance Codeunknown
系列2351
输入调节STANDARD
JESD-30 代码R-PDSO-G24
长度8.2 mm
逻辑集成电路类型LOW SKEW CLOCK DRIVER
功能数量1
反相输出次数
端子数量24
实输出次数10
最高工作温度70 °C
最低工作温度
输出特性3-STATE WITH SERIES RESISTOR
封装主体材料PLASTIC/EPOXY
封装代码SSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, SHRINK PITCH
认证状态Not Qualified
Same Edge Skew-Max(tskwd)0.5 ns
座面最大高度2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
温度等级COMMERCIAL
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
宽度5.3 mm
最小 fmax100 MHz
Base Number Matches1

文档预览

下载PDF文档
October 2005
rev 0.2
ASM2P2351AH
1-Line To 10-Line Clock Driver With 3-State Outputs
Features
Low Output Skew, Low Pulse Skew for Clock-
Distribution and Clock-Generation Applications.
Operates at 3.3V Supply Voltage
.
LVTTL-Compatible Inputs and Outputs.
Supports Mixed-Mode Signal Operation.
(5V Input and Output Voltages With 3.3V Supply
Voltage).
Distributes One Clock Input to Ten Outputs.
Outputs have Internal Series Damping Resistor
to Reduce Transmission Line Effects.
Distributed
V
CC
and
Ground
Pins
Reduce
Switching Noise.
Package Options Include Plastic Small-Outline
and Shrink Small-Outline Packages.
Product Description
The ASM2P2351AH is a high-performance clock-driver
circuit that distributes one input (A) to ten outputs (Y)
with minimum skew for clock distribution. The output-
enable (OE) input disables the outputs to a high-
impedance state. Each output has an internal series
damping resistor to improve signal integrity at the load.
The ASM2P2351AH operates at nominal 3.3V Supply
Voltage.
The propagation delays are adjusted at the factory
using the P0 and P1 pins. The factory adjustments
ensure that the part-to-part skew is minimized and is
kept within a specified window. Pins P0 and P1 are not
intended for customer use and should be connected to
GND.
The ASM2P2351AH is characterized for operation
from 0
°
C to 70
°
C.
Logic Diagram (Positive Logic)
5
OE
23
21
19
18
6
A
7 8
PO P1
16
14
11
9
4
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
2
Y10
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.

 
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