R
EM MICROELECTRONIC-MARIN SA
A3024
Very Low Power 8-Bit 32 kHz RTC with
Digital Trimming, User RAM and High Level Integration
Features
n
Digital trimming and temperature compensation
facilities
n
Can be synchronized to 50 Hz or nearest s/min
n
50 ns access time with 50 pF load capacitance
n
Standby on power down typically 1.2
m
A
n
Universal interface compatible with both Intel and Motorola
n
Simple 8 bit interface with no delays or busy flags
n
16 bytes of user RAM
n
Power fail input disables during power up / down or reset
n
Bus can be tri-state in power fail mode
n
Wide voltage range, 2.0 V to 5.5 V
n
12 or 24 hour data formats
n
Time to 1/100 of a second
n
Leap year correction and week number calculation
n
Alarm and timer interrupts
n
Programmable interrupts: 10 ms, 100 ms, s or min
n
Sleep mode capability
n
Alarm programmable up to one month
n
Timer measures elapsed time up to 24 hours
n
Temperature range -40 to +85
O
C
n
Packages DIP20 and SO20
Typical Operating Configuration
WR or R/W
RD or DS
IRQ
CPU
Address
Decoder
Description
The A3024 is a low power CMOS real time clock. Standby
current is typically 1.2
m
A and the access time is 50 ns. The
interface is 8 bits with multiplexed address and data bus.
Multiplexing of address and data is handled by the input line
A/D. There are no busy flags in the A3024, internal time update
cycles are invisible to the user’s software. Time data can be
read from the A3024 in 12 or 24 hour data formats. An external
signal puts the A3024 in standby mode. Even in standby, the
A3024 pulls the IRQ pin active low on an internal alarm interrupt.
Calendar functions include leap year correction and week
number calculation. Time precision can be achieved by digital
triming. The A3024 can be synchronized to an external 50 Hz
signal or to the nearest second or minute.
CS
RD
WR
Address Bus
CS
IRQ
RD
X in
WR
A3024
A/D
X out
AD0 to AD7
Data Bus
RAM
Fig. 1
Pin Assignment
DIP20 / SO20
Applications
n
n
n
n
n
Industrial controllers
Alarm systems with periodic wake up
PABX and telephone systems
Point of sale terminals
Automotive electronics
SYNC
PF
AD0
AD1
AD2
AD3
A/D
IRQ
V
SS
X
IN
A3024
NC
AD7
AD6
AD5
AD4
RD
WR
CS
V
DD
X
OUT
Fig. 2
1
R
A3024
Absolute Maximum Ratings
Parameter
Maximum voltage at V
DD
Max. voltage at remaining pins
Min. voltage on all pins
Maximum storage temperature
Minimum storage temperature
Maximum electrostatic discharge
to MIL-STD-883C method 3015
Maximum soldering conditions
Symbol Conditions
V
DDmax
V
max
V
min
T
STOmax
T
STOmin
V
Smax
T
Smax
V
SS
+ 7.0V
V
DD
+ 0.3V
V
SS
- 0.3V
+125
O
C
-55
O
C
1000V
250 C x 10s
O
or electric fields; however, it is advised that normal precautions
must be taken as for any other CMOS component. Unless
otherwise specified, proper operation can only occur when all
terminal voltages are kept within the supply voltage range.
Unused inputs must always be tied to a defined logic voltage
level.
Operating Conditions
Parameter
Operating temperature
Logic supply voltage
Supply voltage dv/dt
(power-up & down)
Decoupling capacitor
Crystal Characteristics
Frequency
Load Capacitance
Series resistance
Symbol Min. Typ. Max. Units
T
A
V
DD
dv/dt
100
f
C
L
R
S
32.768
8.2 12.5
35
50
-40
2.0
+85
5.0 5.5
6
O
C
V
Table 1
Stresses above these listed maximum ratings may cause
permanent damage to the device. Exposure beyond specified
operating conditions may affect device reliability or cause
malfunction.
V/
m
s
nF
kHz
pF
kW
Table 2
Handling Procedures
This device has built-in protection against high static voltages
7
Electrical Characteristics
V
DD
= 5.0V ± 10%, V
SS
= 0 V, T
A
= -40 to +85
O
C, unless otherwise specified
Parameter
Standby current
1)
Symbol Test Conditions
I
DD
I
DD
V
DD
= 3 V, PF = 0
V
DD
= 5 V, PF = 0
CS = 4 MHz, RD = V
SS
,
WR = V
DD
I
OL
= 8 mA
I
OH
= 1 mA, V
DD
= 2 V
T
A
= +25
0
C
T
A
= +25
0
C
I
OL
= 6 mA
I
OH
= 6 mA
T
A
= +25 C
V
ILS
= 0.8 V
V
SS
<V
IN
<V
DD
CS = 1
T
A
³
+25
O
C
0
Min.
Typ.
1.2
2
Max.
10
15
1.5
Units
mA
mA
mA
Dynamic current
2)
IRQ (open drain)
Output low voltage
Output low voltage
Inputs and Outputs
Input logic low
Input logic high
Output logic low
Output logic high
PF activation voltage
PF hysteresis
Pullup on SYNC
Input leakage
Output tri-state leakage
Oscillator Characteristics
Starting voltage
Start-up time
Frequency Characteristics
Frequency tolerance
Frequency stability
Temperature stability
1)
V
OL
V
OL
0.4
0.4
V
V
V
IL
V
IH
V
OL
V
OH
V
PFL
V
H
I
LS
I
IN
I
TS
V
STA
V
STA
T
STA
Df/f
f
sta
t
sta
0.8
×
V
DD
2.4
0.5
×
V
DD
100
20
10
10
2
2.5
1
0.2
×
V
DD
0.4
1000
1000
V
V
V
V
V
mV
mA
nA
nA
V
V
s
T
A
= +25 C addr. 10 hex = 00 hex
3)
2.0
£
V
DD
£
5.5 V
addr. 10 hex = 00 hex
O
210
1
see Fig. 5
4)
251
5
ppm
ppm/V
ppm
Table 3
2)
3)
4)
With PFO = 0 (V
SS
) all I/O pads can be tri-state, tested.
With PFO = 1 (V
DD
), CS = 1 (V
DD
) and all other I/O pads fixed to V
DD
or to V
SS
: same standby current, not tested.
All other inputs to V
DD
and all outputs open.
At a given temperature.
See Fig. 4
2
R
A3024
Typical Standby Current at V
DD
= 5 V
I
DD
[
m
A]
5
4
3
2
1
0
-50
25
50
80
95
T
A
[ C]
Fig. 3
0
Typical standby current range at V
DD
= 5 V
Typical Frequency on IRQ
DF
ppm
F
0
250
200
150
100
50
0
-50
-30
-10
10
30
50
70
90
Address 10 hex = 00 hex
Quartz recommended
32.768 Hz ± 30 ppm
with 8.2 pF load capacitance
T
A
[
0
C]
Fig. 4
Characteristic of a Quartz
DF
F
0
[ppm]
-100
DF
ppm
2
= - 0.038
O
2
(T - T
O
) ±10%
F
O
C
DF/F
O
= the ratio of the change in frequency to the nominal value
expressed in ppm (It can be thought of as the frequency
deviation at any temperature.)
O
= the temperature of interest in C
T
O
T
O
= the turnover temperature (25 ±5 C)
To determine the clock error (accuracy) at a given temperature, add
O
the frequency tolerance at 25 C to the value obtained from the
formula above.
T
O
-100
T
O
- 50
T
O
O
Frequency ratio [ppm]
ma
x.
-200
-300
-400
T
O
+50
Temperature [ C]
T
O
+100
T [
O
C]
min
.
Fig. 5
3
R
A3024
Timing Characteristics
V
DD
= 5.0 ± 10%, V
SS
= 0 V, and T
A
= -40 to +85 C
Parameter
Chip select duration, write cycle
Write pulse duration
Time between two transfers
1)
RAM access time
2)
Data valid to Hi-impedance
3)
Write data settle time
4)
Data hold time
Advance write time
PF response delay
Rise time (all timing waveform signals)
Fall time (all timing waveform signals)
5)
CS delay after A/D
CS delay to A/D
1)
0
Symbol
t
CS
t
WR
t
W
t
ACC
t
DF
t
DW
t
DH
t
ADW
t
PF
t
R
t
F
t
A/Ds
t
A/Dt
Test Conditions
Min.
50
50
100
Typ.
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4
C
LOAD
= 50 pF
10
50
10
10
50
30
60
40
100
200
200
5
10
t
ACC
starts from RD (DS) or CS, whichever activates last
Typically, t
ACC
= 5 + 0.9 C
EXT
in ns; where C
EXT
(external parasitic capacitance) is in pF
t
DF
starts from RD (DS) or CS, whichever deactivates first
t
DW
ends at WR (R/W) or CS, whichever deactivates first
t
DH
starts from WR (R/W) or CS, whichever deactivates first
A/D must come before a CS and RD or a CS and WR combination. The user has to guarantee this.
2)
3)
4)
5)
Timing Waveforms
Read Timing for Intel (RD and WR pulse) and Motorola (DS or RD pin tied to CS, and R/W)
t
F
CS
t
A/Ds
A/D
t
CS
t
R
t
W
t
A/Dt
RD/DS
t
ACC
t
DF
DATA
DATA VALID
Fig. 6a
4
R
A3024
Intel Interface
Write Timing
t
CS
CS
t
A/Ds
A/D
RD
t
WR
WR
t
DW
DATA
t
DH
Fig. 6b
t
A/Dt
t
W
DATA VALID
Write
CS
RD
WR
A/D
Valid Address
Valid Data
Fig. 6c
Data Bus
D0 to D7
Read
CS
RD
WR
A/D
Valid Address
Valid Data
Fig. 6d
Data Bus
D0 to D7
5
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