Datasheet> 器件分类 > 无线/射频/通信> 电信电路> 92HD92B2X5NLGXYYX

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92HD92B2X5NLGXYYX: 产品描述Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48; 产品类别无线/射频/通信电信电路; 文件大小4MB，共309页; 制造商IDT (Integrated Device Technology); 标准

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92HD92B2X5NLGXYYX概述

Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48

92HD92B2X5NLGXYYX规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
零件包装代码	QFN
包装说明	ROHS COMPLIANT, QFN-48
针数	48
Reach Compliance Code	compliant
JESD-30 代码	S-XQCC-N48
JESD-609代码	e3
长度	7 mm
湿度敏感等级	3
功能数量	1
端子数量	48
最高工作温度	70 °C
最低工作温度
封装主体材料	UNSPECIFIED
封装代码	HVQCCN
封装形状	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	260
座面最大高度	1 mm
标称供电电压	1.8 V
表面贴装	YES
电信集成电路类型	TELECOM CIRCUIT
温度等级	COMMERCIAL
端子面层	MATTE TIN
端子形式	NO LEAD
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	7 mm
Base Number Matches	1

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DATASHEET

SINGLE CHIP PC AUDIO SYSTEM

CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO+I2S

92HD92

Features

•

4 Channels (2 stereo DACs and 2 stereo ADCs)

with 24-bit resolution

•

Supports full-duplex stereo audio and simultaneous

VoIP

Provides a mono output

2.1 audio crossover support

Description

The 92HD92 single-chip audio system is a low power

optimized, high fidelity, 4-channel audio codec with

integrated speaker amplifier, capless headphone amplifier,

and low drop out voltage regulator.

Dual High Definition Audio and I2S Interfaces allow for

docking and secondary audio support with a single codec.

The integrated combo jack allows for dual-function

headphone and headset detection.

The integrated high-pass and band-pass filters allow for

Hardware EQ and speaker protection.

The high integration of the 92HD92 enables the smallest

PCB footprint with the lowest system audio BOM count and

cost.

The 92HD92 provides high quality HD Audio capability to

notebook and business desktop PC applications.

•

2W/channel Class-D stereo BTL speaker amplifier

@ 4 ohms and 5V

•

10 band hardware parametric equalizer

Hardware compressor limiter

•

Capless headphone amplifier with charge

pump/LDO

I2S support (2 input, 1 output)

Aux Audio Mode with I2C

Combo Jack Support allowing for dual-function

headphone and headset detection

Speaker Protection

•

Dedicated BTL high pass filter

Mono bandpass filter

•

Full HDA015-B low power support

Internal digital core LDO voltage regulator

Microsoft WLP desktop premium logo compliant

Dual SPDIF for WLP compliant support of

simultaneous HDMI and SPDIF output

Support for 1.5V and 3.3V HDA signaling

Two digital microphone inputs (mono, stereo, or

quad microphones)

High performance analog mixer

2 adjustable VREF Out pins for analog microphone

bias

3 analog ports with port presence detect (2 single

ended, 1 BTL)

Digital PC Beep support

48-pad QFN RoHS package

IDT CONFIDENTIAL

V 1.3 6/12

92HD92

92HD92

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

TABLE OF CONTENTS

1. DESCRIPTION ........................................................................................................................ 11

1.1. Overview ..........................................................................................................................................11

1.2. Orderable Part Numbers ..................................................................................................................11

2. DETAILED DESCRIPTION ..................................................................................................... 12

2.1. Port Functionality .............................................................................................................................12

2.1.1. Port Characteristics ............................................................................................................12

2.1.2. Vref_Out .............................................................................................................................14

2.1.3. Jack Detect ........................................................................................................................14

2.1.4. SPDIF Output .....................................................................................................................14

2.2. Mono Output ....................................................................................................................................16

2.3. Mono output Band-Pass Filter .........................................................................................................17

2.3.1. Filter Description ................................................................................................................17

2.4. Mixer ................................................................................................................................................17

2.5. ADC Multiplexers .............................................................................................................................17

2.6. Power Management .........................................................................................................................17

2.7. AFG D0 ............................................................................................................................................18

2.8. AFG D1 ............................................................................................................................................19

2.9. AFG D2 ............................................................................................................................................19

2.10. AFG D3 ..........................................................................................................................................19

2.10.1. AFG D3cold .....................................................................................................................19

2.11. Vendor Specific Function Group Power States D4/D5 ..................................................................19

2.12. Low-voltage HDA Signaling ...........................................................................................................20

2.13. Multi-channel capture ....................................................................................................................20

2.14. EAPD .............................................................................................................................................22

2.15. Digital Microphone Support ...........................................................................................................25

2.16. Analog PC-Beep ............................................................................................................................29

2.17. Digital PC-Beep .............................................................................................................................31

2.18. Headphone Drivers ........................................................................................................................32

2.19. BTL Amplifier .................................................................................................................................32

2.20. BTL Amplifier High-Pass Filter .......................................................................................................32

2.20.1. Filter Description ..............................................................................................................33

2.21. EQ ..................................................................................................................................................33

2.22. Combo Jack Detection ...................................................................................................................33

2.23. GPIO ..............................................................................................................................................34

2.23.1. GPIO Pin mapping and shared functions .........................................................................34

2.23.2. SPDIF/Digital Microphone/GPIO Selection ......................................................................34

2.23.3. Digital Microphone/GPIO Selection .................................................................................34

2.24. HD Audio HDA015-B support ........................................................................................................34

2.25. Digital Core Voltage Regulator ......................................................................................................35

2.26. Digital Audio Port (I2S) ..................................................................................................................36

2.26.1. Characteristics .................................................................................................................36

2.26.2. Left Justified Audio Interface ............................................................................................38

2.26.3. Right Justified Audio Interface (assuming n-bit word length) ...........................................38

2.26.4. I2S Format Audio Interface ..............................................................................................38

2.27. Microphone Mute Input ..................................................................................................................38

2.28. Aux Audio Support .........................................................................................................................40

2.28.1. General conditions in Aux Audio Mode: ...........................................................................40

2.28.2. Entering Aux Audio Mode ................................................................................................41

2.28.3. Firmware/Software Requirements: ...................................................................................41

2.28.4. Part Options Supporting I2S I/O ......................................................................................42

2.28.5. “Playback Path” Port Behavior (Digital I/O) ......................................................................42

2.28.6. When Port E presence detect = 0 ....................................................................................42

2.28.7. When Port E presence detect = 1 ....................................................................................42

2.28.8. “Record Path” Port Behavior (Digital I/O) .........................................................................43

2.28.9. EAPD ...............................................................................................................................44

2.28.10. Class-D BTL Issues .......................................................................................................44

2.28.11. Firmware/Software Requirements: .................................................................................44

2.28.12. SYSTEM DIAGRAMS ....................................................................................................45

IDT CONFIDENTIAL

V 1.3 6/12

92HD92

92HD92

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

2.28.13. I2C control interface .......................................................................................................47

2.28.14. Register Write Cycle ......................................................................................................47

2.28.15. Multiple Write Cycle .......................................................................................................47

2.29. Register Read Cycle ......................................................................................................................48

2.29.1. Multiple Read Cycle .........................................................................................................48

2.29.2. I2C Registers ...................................................................................................................49

3. CHARACTERISTICS ............................................................................................................... 72

3.1. Electrical Specifications ...................................................................................................................72

3.1.1. Absolute Maximum Ratings ...............................................................................................72

3.1.2. Recommended Operating Conditions ................................................................................72

3.2. 92HD92 Analog Performance Characteristics

(PRELIMINARY) ......................................................................73

3.3. Class-D BTL Amplifier Performance ................................................................................................76

3.4. Capless Headphone Supply Characteristics ....................................................................................77

3.5. AC Timing Specs .............................................................................................................................77

3.5.1. HD Audio Bus Timing .........................................................................................................77

3.5.2. SPDIF Timing .....................................................................................................................78

3.5.3. Digital Microphone Timing .................................................................................................78

3.5.4. GPIO Characteristics .........................................................................................................78

3.5.5. I2S Interface Timing ...........................................................................................................79

4. FUNCTIONAL BLOCK DIAGRAM .......................................................................................... 80

5. WIDGET DIAGRAM ................................................................................................................ 81

6. PORT AND PIN CONFIGURATIONS ..................................................................................... 82

6.1. Port Configurations ..........................................................................................................................82

6.2. Pin Configuration Default Register Settings .....................................................................................83

7. WIDGET INFORMATION ........................................................................................................ 84

7.1. Widget List .......................................................................................................................................85

7.2. Reset Key ........................................................................................................................................86

7.3. Root (NID = 00h): VendorID ............................................................................................................86

7.3.1. Root (NID = 00h): RevID ....................................................................................................87

7.3.2. Root (NID = 00h): NodeInfo ...............................................................................................87

7.4. AFG (NID = 01h): NodeInfo .............................................................................................................88

7.4.1. AFG (NID = 01h): FGType .................................................................................................88

7.4.2. AFG (NID = 01h): AFGCap ................................................................................................89

7.4.3. AFG (NID = 01h): PCMCap ...............................................................................................90

7.4.4. AFG (NID = 01h): StreamCap ............................................................................................91

7.4.5. AFG (NID = 01h): InAmpCap .............................................................................................92

7.4.6. AFG (NID = 01h): PwrStateCap .........................................................................................93

7.4.7. AFG (NID = 01h): GPIOCnt ...............................................................................................94

7.4.8. AFG (NID = 01h): OutAmpCap ..........................................................................................94

7.4.9. AFG (NID = 01h): PwrState ...............................................................................................95

7.4.10. AFG (NID = 01h): UnsolResp ..........................................................................................96

7.4.11. AFG (NID = 01h): GPIO ...................................................................................................96

7.4.12. AFG (NID = 01h): GPIOEn ...............................................................................................97

7.4.13. AFG (NID = 01h): GPIODir ..............................................................................................98

7.4.14. AFG (NID = 01h): GPIOWakeEn .....................................................................................99

7.4.15. AFG (NID = 01h): GPIOUnsol ........................................................................................100

7.4.16. AFG (NID = 01h): GPIOSticky .......................................................................................101

7.4.17. AFG (NID = 01h): SubID ................................................................................................101

7.4.18. AFG (NID = 01h): GPIOPlrty ..........................................................................................102

7.4.19. AFG (NID = 01h): GPIODrive .........................................................................................103

7.4.20. AFG (NID = 01h): DMic ..................................................................................................104

7.4.21. AFG (NID = 01h): DACMode .........................................................................................105

7.4.22. AFG (NID = 01h): ADCMode .........................................................................................106

7.4.23. AFG (NID = 01h): PortUse .............................................................................................107

7.4.24. AFG (NID = 01h): ComJack ...........................................................................................108

7.4.25. AFG (NID = 01h): VSPwrState .......................................................................................109

7.4.26. AFG (NID = 01h): AnaPort .............................................................................................110

7.4.27. AFG (NID = 01h): AnaBTL .............................................................................................111

7.4.28. AFG (NID = 01h): AnaBTLStatus ...................................................................................113

IDT CONFIDENTIAL

V 1.3 6/12

92HD92

92HD92

SINGLE CHIP PC AUDIO SYSTEM, CODEC+SPEAKER AMPLIFIER+CAPLESS HP+LDO

7.4.29. AFG (NID = 01h): AnaCapless .......................................................................................113

7.4.30. AFG (NID = 01h): Reset .................................................................................................116

7.4.31. AFG (NID = 01h): DAC3OutAmp (Mono Out Volume) ...................................................117

7.4.32. AFG (NID = 01h): DAC5OutAmpLeft (AuxMode) ...........................................................118

7.4.33. AFG (NID = 01h): DAC5OutAmpRight (AuxMode) ........................................................118

7.4.34. AFG (NID = 01h): ADC4OutAmpLeft (AuxMode) ...........................................................118

7.4.35. AFG (NID = 01h): ADC4OutAmpRight (AuxMode) ........................................................119

7.4.36. AFG (NID = 01h): I2SCtrl ...............................................................................................120

7.4.37. AFG (NID = 01h): EAPD ................................................................................................121

7.4.38. AFG (NID = 01h): ComboJackTime (Available only on WB revision and beyond) ........124

7.5. PortA (NID = 0Ah): WCap ..............................................................................................................126

7.5.1. PortA (NID = 0Ah): PinCap ..............................................................................................127

7.5.2. PortA (NID = 0Ah): ConLst ...............................................................................................128

7.5.3. PortA (NID = 0Ah): ConLstEntry0 ....................................................................................129

7.5.4. PortA (NID = 0Ah): InAmpLeft ..........................................................................................129

7.5.5. PortA (NID = 0Ah): InAmpRight .......................................................................................130

7.5.6. PortA (NID = 0Ah): ConSelectCtrl ....................................................................................130

7.5.7. PortA (NID = 0Ah): PwrState ...........................................................................................131

7.5.8. PortA (NID = 0Ah): PinWCntrl ..........................................................................................131

7.5.9. PortA (NID = 0Ah): UnsolResp ........................................................................................132

7.5.10. PortA (NID = 0Ah): ChSense .........................................................................................133

7.5.11. PortA (NID = 0Ah): EAPDBTLLR ...................................................................................133

7.5.12. PortA (NID = 0Ah): ConfigDefault ..................................................................................134

7.6. PortB (NID = 0Bh): WCap ..............................................................................................................136

7.6.1. PortB (NID = 0Bh): PinCap ..............................................................................................138

7.6.2. PortB (NID = 0Bh): ConLst ...............................................................................................139

7.6.3. PortB (NID = 0Bh): ConLstEntry0 ....................................................................................140

7.6.4. PortB (NID = 0Bh): ConSelectCtrl ....................................................................................140

7.6.5. PortB (NID = 0Bh): PwrState ...........................................................................................140

7.6.6. PortB (NID = 0Bh): PinWCntrl ..........................................................................................141

7.6.7. PortB (NID = 0Bh): UnsolResp ........................................................................................142

7.6.8. PortB (NID = 0Bh): ChSense ...........................................................................................142

7.6.9. PortB (NID = 0Bh): EAPDBTLLR .....................................................................................143

7.6.10. PortB (NID = 0Bh): ConfigDefault ..................................................................................143

7.7. (NID = 0Ch): Vendor Reserved ......................................................................................................146

7.8. PortD (NID = 0Dh): WCap .............................................................................................................147

7.8.1. PortD (NID = 0Dh): PinCap ..............................................................................................148

7.8.2. PortD (NID = 0Dh): ConLst ..............................................................................................149

7.8.3. PortD (NID = 0Dh): ConLstEntry0 ....................................................................................150

7.8.4. PortD (NID = 0Dh): ConSelectCtrl ...................................................................................150

7.8.5. PortD (NID = 0Dh): PwrState ...........................................................................................151

7.8.6. PortD (NID = 0Dh): PinWCntrl .........................................................................................152

7.8.7. PortD (NID = 0Dh): EAPDBTLLR .....................................................................................152

7.8.8. PortD (NID = 0Dh): ConfigDefault ....................................................................................152

7.9. PortE (NID = 0Eh): WCap (I2S Output) .........................................................................................156

7.9.1. PortE (NID = 0Eh): PinCap ..............................................................................................157

7.9.2. PortE (NID = 0Eh): ConLst ...............................................................................................158

7.9.3. PortE (NID = 0Eh): ConLstEntry0 ....................................................................................159

7.9.4. PortE (NID = 0Eh): OutAmpLeft .......................................................................................159

7.9.5. PortE (NID = 0Eh): OutAmpRight ....................................................................................160

7.9.6. PortE (NID = 0Eh): ConSelectCtrl ....................................................................................160

7.9.7. PortE (NID = 0Eh): PwrState ...........................................................................................161

7.9.8. PortE (NID = 0Eh): PinWCntrl ..........................................................................................162

7.9.9. PortE (NID = 0Eh): UnsolResp ........................................................................................162

7.9.10. PortE (NID = 0Eh): ChSense .........................................................................................163

7.9.11. PortE (NID = 0Eh): EAPDBTLLR ...................................................................................163

7.9.12. PortE (NID = 0Eh): ConfigDefault ..................................................................................164

7.10. PortF (NID = 0Fh): WCap (I2S Input) ..........................................................................................167

7.10.1. PortF (NID = 0Fh): PinCap .............................................................................................168

IDT CONFIDENTIAL

V 1.3 6/12

92HD92

92HD92B2X5NLGXYYX相似产品对比

	92HD92B2X5NLGXYYX	92HD92B1X5NLGXYYX8	92HD92B1X5NLGXYYX	92HD92B2X5NLGXYYX8
描述	Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48	Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48	Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48	Telecom Circuit, 1-Func, ROHS COMPLIANT, QFN-48
是否无铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合
零件包装代码	QFN	QFN	QFN	QFN
包装说明	ROHS COMPLIANT, QFN-48	ROHS COMPLIANT, QFN-48	ROHS COMPLIANT, QFN-48	ROHS COMPLIANT, QFN-48
针数	48	48	48	48
Reach Compliance Code	compliant	compliant	compliant	compliant
JESD-30 代码	S-XQCC-N48	S-XQCC-N48	S-XQCC-N48	S-XQCC-N48
JESD-609代码	e3	e3	e3	e3
长度	7 mm	7 mm	7 mm	7 mm
湿度敏感等级	3	3	3	3
功能数量	1	1	1	1
端子数量	48	48	48	48
最高工作温度	70 °C	70 °C	70 °C	70 °C
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装代码	HVQCCN	HVQCCN	HVQCCN	HVQCCN
封装形状	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）	260	260	260	260
座面最大高度	1 mm	1 mm	1 mm	1 mm
标称供电电压	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES
电信集成电路类型	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	MATTE TIN	MATTE TIN	MATTE TIN	MATTE TIN
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子节距	0.5 mm	0.5 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	30	30	30	30
宽度	7 mm	7 mm	7 mm	7 mm
Base Number Matches	1	1	1	1

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