DATA SHEET
Integrated
DDR SDRAM MUX
Circuit
Systems, Inc.
DDR SDRAM MUX
F
EATURES
•
40 low skew single-ended DIMM ports
•
4 SSTL-2 compatible enable inputs
•
Maximum Switching Speed: 3ns
•
Output skew: 120ps (maximum)
•
Bank skew: 60ps (maximum)
•
r
on
= 8Ω (typical)
•
Full 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Pin compatible with the CBTV4010
ICS83840B
ICS83840B
G
ENERAL
D
ESCRIPTION
The ICS83840B is a DDR SDRAM MUX and is
a member of the HiPerClockS™ family of High
HiPerClockS™
Performance Clock Solutions from ICS. The de-
vice has 10 Host Lines and each host line can
be passed to 4 Data Ports. The 10 channels are
allocated as follows in the DDR SDRAM appli-
cation: 8 data lines, 1 strobe line and 1 DQm line. The Host/
Data Ports are compatible with single-ended SSTL-2 and the
device operates from a 2.5V supply.
ICS
Guaranteed low output skew makes the ICS83840B ideal
for demanding applications which require well defined per-
formance and repeatability.
S
IMPLIFIED
S
CHEMATIC
L
OGIC
D
IAGRAM
HP0
R
ON
Sw
Sw
Sw
0DP0
1DP0
2DP0
Sw
3DP0
HPx
nDPx
400Ω
HP9
R
ON
Sw
Sw
Sw
Sw
0DP9
1DP9
2DP9
3DP9
nSn
SW
nS0
nS1
nS2
nS3
P
IN
A
SSIGNMENT
1
A
B
C
D
E
F
G
H
J
K
L
2DP9
1DP9
0DP9
1DP8
0DP8
3DP7
V
DD
nS2
nc
2
nS1
V
DD
nS3
GND
3DP9
HP9
3DP8
2DP8
HP8
GND
2DP7
3
nc
nS0
4
GND
5
1DP0
0DP0
6
2DP0
HP0
7
3DP0
0DP1
8
1DP 1
9
2DP1
HP1
10
3DP 1
GND
HP 2
3DP2
0DP 3
HP3
GND
0DP4
HP4
11
0DP2
1DP2
2DP2
1DP3
2DP3
3DP3
1DP4
2DP4
0DP5
REV. A JANUARY 30, 2004
ICS83840B
64-Ball TFBGA
7mm x 7mm x 1.2mm
package body
H Package
Top View
HP7
1DP7
0DP7
3DP6
2DP6
HP6
1DP6
GND
0DP6
3DP 5
HP 5
2DP5
3DP4
1DP5
83840BH
www.icst.com/products/hiperclocks.html
1
IDT™ / ICS™
DDR SDRAM MUX
ICS83840B
1
ICS83840B
Circuit
DDR SDRAM MUX
Integrated
Systems, Inc.
ICS83840B
DDR SDRAM MUX
TSD
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
A1, B2
B4, B10, D2, G10, K2, K7
A3, C1
A2, B1, C2, B3
B6, B9, C10, F2, F10,
J2, J10, K3, K6, K9
A5, A6, A7, B5
A9, A10, B7, B8
A11, B11, C11, D10
E10, E11, F11, G11
H10, J11, K10, K11
K8, L9, L10, L11
K5, L5, L6, L7
K4, L1, L2, L3
G2, H2, J1, K1
E1, E2, F1, G1
Name
V
DD
GN D
nc
nS1, nS2, nS3, nS0
HP0, HP1, HP2, HP9, HP3,
HP8, HP4, HP7, HP6, HP5
1DP0, 2DP0, 3DP0, 0DP0
2DP1, 3DP1, 0DP1, 1DP1
0DP2, 1DP2, 2DP2, 3DP2
ODP3, 1DP3, 2DP3, 3DP3
0DP4, 1DP4, 3DP4, 2DP4
3DP5, 2DP5, 1DP5, 0DP5
3DP6, 2DP6, 1DP6, 0DP6
0DP7, 3DP7, 2DP7, 1DP7
3DP8, 2DP8, 1DP8, 0DP8
2DP9, 3DP9, 1DP9, 0DP9
Type
Power
Power
Unused
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Por t
Description
Positive supply pins.
Power supply ground.
No connect.
Select pins.
Host por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
DIMM por ts.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol Parameter
C
IN
C
ON
Input Capacitance
Channel on Capacitance
nSx
HPx
Test Conditions
V
I
= 0V or V
DD
V
IN
= 1.5V
Minimum
Typical
Maximum
5
14
Units
pF
pF
NOTE: Capacitance values are measured at 10MHz and a bias voltage 3V. Capacitance is not production tested.
T
ABLE
3. F
UNCTION
T
ABLE
Control Input
nSx
L
H
Function
Host Por t = DIMM Por t
Host Por t = Disconnected
DIMM Por t = 400
Ω
to GND
83840BH
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 30, 2004
IDT™ / ICS™
DDR SDRAM MUX
2
ICS83840B
ICS83840B
Circuit
DDR SDRAM MUX
Integrated
Systems, Inc.
ICS83840B
DDR SDRAM MUX
TSD
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Ports
DC Input Clamp Current, I
IK
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
-50mA
50.04°C/W (0 mfps)
-65°C to 150°C
-0.5V to +3.3V
-0.3V to V
DD
+ 0.3 V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
DD
I
DD
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.3
Typical
2.5
Maximum
2.7
50
Units
V
µA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
V
IK
I
L
Input High Voltage
Input Low Voltage
Input Clamp Voltage
nSx
Input Leakage
Current
Host Por t
DIMM Por t
r
ON
On Resistance; NOTE 1
nSx
nSx
V
DD
= 2.3V; I
I
= -18mA
V
DD
= 2.5V; V
I
= V
DD
or GND;
nS = V
DD
nS = GND for I
IL(test)
V
DD
= 2.5V; V
A
= 0.8V; V
B
= 1.0V
5
8
Test Conditions
Minimum
1.6
0.9
-1.2
±100
±100
±100
13
Typical
Maximum
Units
V
V
V
µA
µA
µA
Ω
5
8
13
V
DD
= 2.5V; V
A
= 1.7V; V
B
= 1.5V
Ω
NOTE 1: Calculated from the current measure, between the Host and the DIMM terminals at the indicated voltages on
each side of the switch.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
From HPx or xDPx to
t
PD
80
160
250
ps
NOTE 1, 4
xDPx or HPx
Output
From nSx to
1.2
ns
t
EN
Enable Time
HPx or nDPx
Output
From nSx to
t
DIS
1.2
ns
Disable Time
HPx or nDPx
Output Skew;
Any Por t to any Por t
120
ps
t
OSK
NOTE 2, 4
Bank Skew;
Any Por t to any Por t
60
ps
t
BSK
NOTE 3, 4
within the same bank
NOTE 1: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Not production tested, guaranteed by characterization.
83840BH
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 30, 2004
IDT™ / ICS™
DDR SDRAM MUX
3
ICS83840B
ICS83840B
Circuit
DDR SDRAM MUX
Integrated
Systems, Inc.
ICS83840B
DDR SDRAM MUX
TSD
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
= 1.25V ± 0.1V
V
DD
SCOPE
nDPx
V
DD
2
LVCMOS
GND
Qx
V
DD
nDPy
2
t
sk(o)
-1.25V ± 0.1V
This circuit is used for test purposes only,
not
intended for application use.
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
XDP0:XDP9
V
DD
2
Sn
(Low-level
enabling)
2.5V
1.25V
1.25V
0V
XDP0:XDP9
V
DD
2
t
sk(o)
t
PZH
→
Output nDPx
(See Note)
1.25V
t
PHZ
→
←
V
OH
V
OH
- 0.15V
V
OL
NOTE: The output is high except when disabled by the Sn control.
B
ANK
S
KEW
(
where X denotes outputs in the same bank
)
3-S
TATE
O
UTPUT
E
NABLE
/D
ISABLE
T
IMES
D or H
V
DD
2
H or D
t
PD
V
DD
2
P
ROPAGATION
D
ELAY
83840BH
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 30, 2004
IDT™ / ICS™
DDR SDRAM MUX
4
ICS83840B
ICS83840B
Circuit
DDR SDRAM MUX
Integrated
Systems, Inc.
ICS83840B
DDR SDRAM MUX
TSD
R
ELIABILITY
I
NFORMATION
T
ABLE
6.
θ
JA
VS
. A
IR
F
LOW
T
ABLE
θ
JA
by Velocity (Millimeter Feet per Second)
0
Two-Layer PCB, JEDEC Standard Test Boards
50.04°C/W
1
43.18°C/W
2
41.17°C/W
NOTE:
Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
RANSISTOR
C
OUNT
The transistor count for ICS83840B is: 320
83840BH
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 30, 2004
IDT™ / ICS™
DDR SDRAM MUX
5
ICS83840B
FPGA/CPLD
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