Synchronous Ethernet Frequency
Translator
ICS840272I
DATA SHEET
General Description
The ICS840272I is a PLL-based Frequency Translator intended for
use in Synchronous Ethernet applications. This high performance
device is optimized to generate 25MHz and 8kHz LVCMOS clock
outputs. The ICS840272I accepts the following differential or
single-ended input signals: 161.1328125MHz (10GbE Mode),
156.25MHz (1GbE Mode), or 125MHz (Recovered clock from
10/100/1000BaseT Ethernet PHY). The extended temperature
range supports telecommunication and networking end equipment
requirements.
Features
•
•
•
•
•
•
Two single-ended outputs (LVCMOS or LVTTL levels),
output impedance: 17
Single-ended lock detect output (LVCMOS or LVTTL levels)
Two selectable differential clock inputs
Differential input pair (CLKx, nCLKx) accepts LVPECL, LVDS,
LVHSTL, SSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Selectable input frequencies: 161.1328MHz, 156.25MHz or
125MHz
Output frequency: 25MHz, 8kHz
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Pin Assignment
V
DD
LOCK_DT
REF_SEL
SEL0
SEL1
OE
V
DDA
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DDO
QA
QB
GND
CLK0
nCLK0
CLK1
nCLK1
•
•
•
•
ICS840272I
16-Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Top View
Block Diagram
LOCK_DT
CLK0
Pulldown
0
0
nCLK0
Pullup/Pulldown
CLK1
Pulldown
Pullup/Pulldown
N
P
PLL
1
QA
25MHz
1
QB
8kHz
nCLK1
REF_SEL
Pulldown
M
Input Control
SEL[1:0]
Pulldown:Pullup
00 = PLL Bypass, 25MHz Input
01 = 161.1328125MHz (default)
10 = 156.25MHz
11 = 125MHz
OE
Pulldown
ICS840272I REVISION A 06/19/14
1
©2014 Integrated Device Technology, Inc.
ICS840272I DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
V
DD
LOCK_DT
REF_SEL
SEL0
SEL1
OE
V
DDA
GND
nCLK1
CLK1
nCLK0
CLK0
GND
QB
QA
V
DDO
Power
Output
Input
Input
Input
Input
Power
Power
Input
Input
Input
Input
Power
Output
Output
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pulldown
Type
Description
Core supply pin.
Lock detect. Logic HIGH when PLL is locked.
Selects the input reference clock. When LOW, selects CLK0, nCLK0.
When HIGH, selects CLK1, nCLK1. LVCMOS/LVTTL interface levels.
Selects the input reference frequency and the PLL bypass mode. See
Table
3A.
LVCMOS/LVTTL interface levels.
Selects the input reference frequency and the PLL bypass mode. See
Table
3A.
LVCMOS/LVTTL interface levels.
8kHz output enable pin. When LOW, QB is disabled. When HIGH, QB is
enabled. LVCMOS/LVTTL interface levels. See
Table 3B.
Analog supply pin.
Power supply ground.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Non-inverting differential clock input.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output supply pin.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.465V
Test Conditions
Minimum
Typical
4
51
51
17
Maximum
Units
pF
k
k
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
2
REVISION A 06/19/14
ICS840272I DATA SHEET
Function Tables
Table 3A. SEL[1:0] Function Table
Inputs
SEL1
0
0 (default)
1
1
SEL0
0
1 (default)
0
1
CLKx, nCLKx (MHz)
25
161.1328125
156.25
125
Function
Mode
PLL Bypass
PLL Enabled
PLL Enabled
PLL Enabled
Output (MHz)
QA
25
25
25
25
Table 3B. OE Function Table
Control Input
OE
0 (default)
1
Function
QB Output
Disabled (High impedance)
Enabled
REVISION A 06/19/14
3
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
ICS840272I DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
81.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.11
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
57
11
5
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OE, SEL1,
REF_SEL
SEL0
OE, SEL1,
REF_SEL
SEL0
V
OH
V
OL
Output High Voltage
Output Low Voltage
Test Conditions
V
DD
= 3.465V
V
DD
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
I
OH
= -12mA
I
OL
= 12mA
-5
-150
2.6
0.5
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
V
V
Input High Current
I
IL
Input Low Current
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
4
REVISION A 06/19/14
ICS840272I DATA SHEET
Table 4C. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
CLK[0:1],
nCLK[0:1]
CLK[0:1]
Input Low Current
nCLK[0:1]
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit(Ø)
tjit(cc)
t
R
/ t
F
Parameter
QA
Output Frequency
QB
RMS Phase Jitter
(Random); NOTE 1
Cycle-to-Cycle Jitter
Output Rise/Fall Time
QB
QA
odc
Output Duty Cycle
QB
47
53
%
20% to 80%
450
47
1100
53
ps
%
QA
QA
QA
25MHz, Integration Range:
12kHz – 10MHz
25MHz
20% to 80%
450
8
1.1
37
1100
kHz
ps
ps
ps
Test Conditions
Minimum
Typical
25
Maximum
Units
MHz
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to Phase Noise plot.
REVISION A 06/19/14
5
SYNCHRONOUS ETHERNET FREQUENCY TRANSLATOR
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