FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL FREQUENCY SYNTHESIZER
ICS840004
G
ENERAL
D
ESCRIPTION
The ICS840004 is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Ether net
HiPerClockS™
reference clock frequencies and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from IDT. Using a 26.5625MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz. The ICS840004 uses IDT’s 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typical
random r ms phase jitter, easily meeting Ethernet jitter
requirements. The ICS840004 is packaged in a small 20-pin
TSSOP package.
F
EATURES
• Four LVCMOS/LVTTL outputs, 17Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 700MHz
• RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.49ps typical, V
DDO
= 3.3V
Phase noise:
Offset
Noise Power
100Hz ............... -88.8 dBc/Hz
1kHz ............. -109.0 dBc/Hz
10kHz ............. -116.1 dBc/Hz
100kHz ............. -117.5 dBc/Hz
• Full 3.3V or mixed 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input Frequency
(MHz)
26.5625
26.5625
26.5625
26.5625
26.04166
Inputs
M Divider
F_SEL0
Value
0
24
1
0
1
1
24
24
24
24
N Divider
Value
3
4
6
12
4
F_SEL1
0
0
1
1
0
M/N Ratio
Value
8
6
4
2
6
Output Frequency
Range (MHz)
212.5
159.375
106.25
53.125 (default)
156.25
B
LOCK
D
IAGRAM
OE
Pullup
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
Pulldown
P
IN
A
SSIGNMENT
2
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
XTAL_IN 26.5625MHz
OSC
XTAL_OUT
REF_CLK Pulldown
0
F_SEL1:0
1
Phase
Detector
00
01
10
11
Q0
1
VCO
0
N
÷3
÷4
÷6
÷12
(default)
Q1
ICS840004
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
Q2
M = ÷24 (fixed)
Q3
G Package
Top View
MR
Pulldown
IDT
™
/ ICS
™
LVCMOS FREQUENCY SYNTHESIZER
1
ICS840004AG REV B February 25, 2009
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 9
3
4
5
6
Name
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
Input
Unused
Input
Input
Input
Input
Pulldown
Pulldown
Pullup
Pulldown
Type
Pullup
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
Selects between the cr ystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL reference clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17
Ω
typical output impedance.
Output supply pin.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
7
8
10
11,
12
13, 19
14, 15
17, 18
16
20
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
V
DDO
F_SEL1
Input
Power
Power
Input
Power
Output
Power
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
Test Conditions
Minimum
Typical
4
8
51
51
17
21
Maximum
Units
pF
pF
kΩ
kΩ
Ω
Ω
IDT
™
/ ICS
™
LVCMOS FREQUENCY SYNTHESIZER
2
ICS840004AG REV B February 25, 2009
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
73.2°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
Typical
3.3
3.3
3.3
2.5
Maximum
3.465
3.465
3.465
2.625
100
12
10
Units
V
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
I
IH
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, REF_CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 3.3V or 2.5V ± 5%
-150
-5
2.6
1.8
0.5
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
V
I
IL
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
23.3
Test Conditions
Minimum
Typical
26.5625
Maximum
29.16
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
IDT
™
/ ICS
™
LVCMOS FREQUENCY SYNTHESIZER
3
ICS840004AG REV B February 25, 2009
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
93.33
46.67
Typical
212.5
159.375
156.25
106.25
0.49
0.55
0.56
0.79
0.65
200
700
59
57
52
Maximum
226.66
170
113.33
56.66
60
212.5MHz (637kHz - 10MHz)
159.375MHz (637kHz - 10MHz)
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
%
t
sk(o)
Output Skew; NOTE 1, 3
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637kHz - 10MHz)
53.125MHz (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
F_SEL[1:0] = 00
41
odc
Output Duty Cycle
F_SEL[1:0] = 01
43
F_SEL[1:0] = 10 or 11
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
Test Conditions
F_SEL[1:0] = 00
f
OUT
Output Frequency
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum
186.67
140
93.33
46.67
Typical
212.5
159.375
156.25
106.25
0.46
0.54
0.57
0.73
0.63
200
700
58
56
52
Maximum
226.66
170
113.33
56.66
60
212.5MHz (637kHz - 10MHz)
159.375MHz (637kHz - 10MHz)
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
%
t
sk(o)
Output Skew; NOTE 1, 3
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637kHz - 10MHz)
53.125MHz (637kHz - 10MHz)
t
R
/ t
F
Output Rise/Fall Time
20% to 80%
F_SEL[1:0] = 00
42
odc
Output Duty Cycle
F_SEL[1:0] = 01
44
F_SEL[1:0] = 10 or 11
48
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
LVCMOS FREQUENCY SYNTHESIZER
4
ICS840004AG REV B February 25, 2009
ICS840004
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
53.125MH
Z
@3.3V
0
-10
-20
-30
-40
-50
➤
Fibre Channel Filter
53.125MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.65ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
➤
1k
10k
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
106.25MH
Z
@3.3V
-10
-20
-30
-40
-50
➤
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 10MHz = 0.79ps (typical)
0
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
Raw Phase Noise Data
O
FFSET
F
REQUENCY
(H
Z
)
IDT
™
/ ICS
™
LVCMOS FREQUENCY SYNTHESIZER
➤
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
10k
5
ICS840004AG REV B February 25, 2009
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