8:1 Differential-to-3.3V or 2.5V
LVPECL/ECL Clock Multiplexer
853S058
DATA SHEET
General Description
The 853S058 is an 8:1 Differential-to-3.3V or 2.5V LVPECL / ECL
Clock Multiplexer which can operate up to 2.5 GHz. The 853S058
has 8 differential selectable clock inputs. The PCLK, nPCLK input
pairs can accept LVPECL, LVDS, SSTL or CML levels. The fully
differential architecture and low propagation delay make it ideal for
use in clock distribution circuits. The select pins have internal
pulldown resistors. The SEL2 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 000 selects PCLK0, nPCLK0).
Features
•
•
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•
•
•
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High speed 8:1 differential muliplexer
One differential 3.3V or 2.5V LVPECL output pair
Eight selectable differential PCLKx, nPCLKx input pairs
Differential PCLKx, nPCLKx pairs can accept the following
interface levels: LVPECL, LVDS, SSTL,CML
Maximum output frequency: 2.5GHz
Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx input
Additive phase jitter, RMS: 0.075ps (typical)
Part-to-part skew: 350ps (maximum)
Propagation delay: 600ps (maximum)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.465V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.465V to -2.375V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
PCLK2
Pulldown
nPCLK2
Pullup/Pulldown
PCLK3
Pulldown
nPCLK3
Pullup/Pulldown
PCLK4
Pulldown
nPCLK4
Pullup/Pulldown
PCLK5
Pulldown
nPCLK5
Pullup/Pulldown
PCLK6
Pulldown
nPCLK6
Pullup/Pulldown
PCLK7
Pulldown
nPCLK7
Pullup/Pulldown
000
(default)
Pin Assignment
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
PCLK7
nPCLK7
PCLK6
nPCLK6
V
CC
Q
nQ
V
EE
PCLK5
nPCLK5
PCLK4
nPCLK4
001
010
011
Q
nQ
100
853S058
24-Lead TSSOP, 173-MIL
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
101
110
111
SEL2
Pulldown
SEL1
Pulldown
SEL0
Pulldown
853S058 REVISION B 1/6/15
1
©2015 Integrated Device Technology, Inc.
853S058 DATA SHEET
Pin Descriptions and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
1
2
3
4
5, 20
6, 7, 8
9
10
11
12
13
14
15
16
17
18, 19
21
22
23
24
Name
PCLK0
nPCLK0
PCLK1
nPCLK1
V
CC
SEL0, SEL1,
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
V
EE
nQ, Q
nPCLK6
PCLK6
nPCLK7
PCLK7
Input
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Output
Input
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Description
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Positive supply pins.
Clock select input pins. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 default when left floating.
Non-inverting differential clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
VCC
/2
Parameter
Input Capacitance
Pulldown Resistor
RPullup/Pulldown Resistor
Test Conditions
Minimum
Typical
2
75
50
Maximum
Units
pF
k
k
8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
2
REVISION B 1/6/15
853S058 DATA SHEET
Function Tables
Table 3. Control Input Function Table
Inputs
SEL2
0 (default)
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
Q
PCLK0
PCLK1
PCLK2
PCLK3
PCLK4
PCLK5
PCLK6
PCLK7
Outputs
nQ
nPCLK0
nPCLK1
nPCLK2
nPCLK3
nPCLK4
nPCLK5
nPCLK6
nPCLK7
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
-40C to +85C
85.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
3.465
55
Units
V
mA
REVISION B 1/6/15
3
8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
853S058 DATA SHEET
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
SEL[0:2]
SEL[0:2]
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
Minimum
2.2
1.7
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 4C. LVPECL DC Characteristics,
V
CC
= 2.375V to 3.465V; V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
V
OH
V
OL
V
SWING
Parameter
Input High
Current
Input Low
Current
PCLK[0:7],
nPCLK[0:7]
PCLK[0:7]
nPCLK[0:7]
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
-10
-150
0.15
1.2
V
CC
– 1.125
V
CC
– 1.895
0.6
1.2
V
CC
V
CC
– 0.875
V
CC
– 1.62
1.0
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
V
V
Peak-to-Peak Input Voltage;
NOTE 1
Common Mode Range;
NOTE 1, 2
Output High Voltage; NOTE 3
Output Low Voltage; NOTE 3
Peak-to-Peak
Output Voltage Swing
NOTE 1: V
IL
should not be less than V
EE
– 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: Outputs terminated with 50
to V
CC
– 2V.
Table 4D. ECL DC Characteristics,
V
CC
= 0V, V
EE
= -3.465V to -2.375V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
PP
V
CMR
I
IH
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage;
NOTE 2
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
High Current
Input
Low Current
PCLK[0:7],
nPCLK[0:7]
PCLK[0:7]
nPCLK[0:7]
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
NOTE 2: V
IL
should not be less than V
EE
– 0.3V.
NOTE 3: Common mode voltage is defined as V
IH
.
8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
4
REVISION B 1/6/15
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V,
V
IN
= 0V
-10
-150
Test Conditions
Minimum
-1.225
-1.895
0.15
V
EE
+ 1.2
Typical
Maximum
-0.935
-1.67
1.2
V
CC
150
Units
V
V
V
V
µA
µA
µA
I
IL
853S058 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= 0V, V
EE
= -3.465V to -2.375V or V
CC
= 2.375 to 3.465V, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit
Parameter
Output Frequency
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
Propagation Delay;
NOTE 1
Part-to-Part Skew;
NOTE 2, 3
Input Skew
Output Rise/Fall Time
MUX Isolation; NOTE 4
20% to 80%
155.52MHz,
Input Peak-to-Peak = 800mV
75
90
155.52MHz, Integration Range:
12kHz – 20MHz
250
0.075
Test Conditions
Minimum
Typical
Maximum
2.5
Units
GHz
ps
t
PD
tsk(pp)
tsk(i)
t
R
/ t
F
MUX
ISOLATION
600
350
75
250
ps
ps
ps
ps
dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured
1.0GHz, unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Q, nQ output measured differentially. See
Parameter Measurement Information
for MUX Isolation diagram.
REVISION B 1/6/15
5
8:1 DIFFERENTIAL-TO-3.3V OR 2.5V LVPECL/ECL
CLOCK MULTIPLEXER
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