LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL
FANOUT BUFFER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
85310I-21
Data Sheet
G
ENERAL
D
ESCRIPTION
T h e 8 5 3 1 0I-21 is a low skew, high performance dual
1-to-5 Differential-to-2.5V/3.3VECL/LVPECL Fanout Buf-
fer. The CLKx, nCLKxpairs can accept most standard
differential input levels.The 85310I-21 is characterized
to operate from either a 2.5V or a 3.3V power supply.
Guaranteed output and part-to-part skew characteris-
tics make the 85310I-21 ideal for those clock distribution
applications demanding well defined performance and repeat-
ability.
F
EATURES
•
Two differential 2.5V/3.3V LVPECL / ECL bank outputs
•
Two differential clock input pairs
•
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 700MHz
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKx input
•
Output skew: 25ps (typical)
•
Part-to-part skew: 270ps (typical)
•
Propagation delay: 1.7ns (typical)
•
Additive phase jitter, RMS: <0.13ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Lead-Free package fully RoHS complaint
•
For replacement part use 8T39S11A
B
LOCK
D
IAGRAM
CLKA
nCLKA
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
P
IN
A
SSIGNMENT
nQA0
nQA1
nQA2
V
CCO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CCO
nQB4
QB4
nQB3
QB3
nQB2
QB2
V
CCO
V
CCO
QA0
QA1
QA2
32 31 30 29 28 27 26 25
V
CC
nc
CLKA
nCLKA
nc
CLKB
24
23
22
QA3
nQA3
QA4
nQA4
QB0
nQB0
QB1
nQB1
ICS85310I-21
21
20
19
18
17
CLKB
nCLKB
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
nCLKB
V
EE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
©2016 Integrated Device Technology, Inc
1
June 24, 2016
85310I-21 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 5
3
4
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
nc
CLKA
nCLKA
CLKB
nCLKB
V
EE
V
CCO
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA4, QA4
nQA3, QA3
nQA2, QA2
nQA1, QA1
nQA0, QA0
Power
Unused
Input
Input
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pullup
Type
Description
Core supply pin.
No connect.
Pulldown Non-inverting differential clock input.
Inverting differential clock input.
Inverting differential clock input.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Pulldown Non-inverting differential clock input.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLKA or CLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLKA or nCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA0:QA4,
QB0:QB4
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQA0:nQA4,
nQB0:nQB4
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information, “Wiring the Differential Input to Accept Single Ended Levels”.
©2016 Integrated Device Technology, Inc
2
June 24, 2016
85310I-21 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
4.6V
-4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
47.9°C/W (0 lfpm)
Operating Temperature Range, TA -40°C to +85°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.8
3.8
120
Units
V
V
mA
T
ABLE
4B. D
IFFERENTIAL
DC C
HARACTERISTICS
,
VV
CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
CLKA, CLKB
nCLKA, nCLKB
CLKA, CLKB
nCLKA, nCLKB
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKA, nCLKA and CLKB, nCLKB is V
CC
+ 0.3V.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V.
©2016 Integrated Device Technology, Inc
3
June 24, 2016
85310I-21 Data Sheet
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 2.375V
TO
3.8V, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
t
R
t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Rise Time
Output Fall Time
Output Duty Cycle
20% to 80%
20% to 80%
200
200
47
ƒ
≤
500MHz
1.7
25
270
<0.13
700
700
53
Test Conditions
Minimum
Typical
Maximum
700
2.2
50
550
Units
MHz
ns
ps
ps
ps
ps
ps
%
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
4
June 24, 2016
85310I-21 Data Sheet
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the fun-
damental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using
a Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in the
0
-10
-20
-30
-40
-50
-60
1Hz band to the power in the fundamental. When the required
offset is specified, the phase noise is called a
dBc
value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter, RMS
@ 155.52MHz = <0.13ps typical
SSB P
HASE
N
OISE
dBc/H
Z
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
©2016 Integrated Device Technology, Inc
5
June 24, 2016
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