PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001-22
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
• One 3.3V LVPECL output pair and one LVCMOS output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 490MHz - 640MHz
• Output frequency range: 490MHz - 640MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.79ps (typical) design target
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS843001-22 is a a highly versatile, low
phase noise LVPECL Synthesizer which can
HiPerClockS™
generate low jitter reference clocks for a variety of
communications applications and is a member of
the HiPerClocks
TM
family of high performance clock
solutions from ICS. The dual crystal interface allows
the synthesizer to support up to two communications standards
in a given application (i.e. 1GB Ethernet with a 25MHz crystal
and 1Gb Fibre Channel using a 25.5625MHz crystal). The rms
phase jitter performance is typically less than 1ps, thus making
the device acceptable for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001-22 is
packaged in a small 24-pin TSSOP package.
ICS
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Control Input
OE
0
1
FLOAT
Q0/nQ0
High-Z
Active
High-Z
Outputs
REF_CLK
High-Z
High-Z
Active
P
IN
A
SSIGNMENT
V
CCO
_
CMOS
N0
N1
N2
V
CCO
_
PECL
Q0
nQ0
V
EE
V
CCA
V
CC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF_CLK
V
EE
OE
M2
M1
M0
MR
SEL1
SEL0
TEST_CLK
XTAL_IN0
XTAL_OUT0
B
LOCK
D
IAGRAM
3
N2:N0
SEL0
Pulldown
SEL1
Pulldown
ICS843001-22
N
000
001
010
011
÷1
÷2
÷3
÷4
(default)
÷5
÷6
÷8
÷10
XTAL_IN0
OSC
XTAL_OUT0
00
11
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q0
nQO
XTAL_IN1
OSC
XTAL_OUT1
TEST_CLK
Pulldown
01
Phase
Detector
VCO
490MHz -640MHz
10
01
00
100
101
110
111
10
000
001
010
011
100
101
M
÷18
÷22
÷24
÷25
÷32
(default)
÷40
MR
M2:M0
Pulldown
3
REF_CLK
OE
Pullup/Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843001AG-22
www.icst.com/products/hiperclocks.html
REV. A JUNE 17, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001-22
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Type
Description
Output supply pin for REF_CLK output.
Output divider select pins. Default value = ÷4.
LVCMOS/LVTTL interface levels.
Pulldown
Output supply pin for Q0/nQ0 LVPECL output.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Analog supply pin.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Pulldown LVCMOS/LVTTL clock input.
Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true output Q0 to go low and the inver ted output nQ0
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Pulldown Feedback divider select pins. Default value = ÷32.
LVCMOS/LVTTL interface levels.
Pullup
Pullup/ 3-State clock output enable, (High/Low/Float). LVCMOS/LVTTL interface
Pulldown levels. See Control Input Function Table for states.
Reference clock output. LVCMOS/LVTTL interface levels.
Pullup
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6, 7
8, 23
9
10
11
12
13
14
15
16, 17
18
19, 20
21
22
24
Name
V
CCO_CMOS
N0, N1
N2
V
CCO_PECL
Q0, nQ0
V
EE
V
CCA
V
CC
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
TEST_CLK
SEL0, SEL1
MR
M0, M1
M2
OE
REF_CLK
Input
Input
Power
Ouput
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Output
Power
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
R
out
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
51
51
15
Maximum
Units
pF
kΩ
kΩ
Ω
843001AG-22
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001-22
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Output Frequency
(MHz)
74.25
70
74.25
200
74.1758245
155.52
77.76
622.08
311.04
156.25
250
125
62.5
100
150
75
106.25
212.5
159.375
187.5
HDTV
SONET
SONET
SONET
SONET
10 GigE
Ethernet
1 GigE
1 GigE
PCI Express
SATA
SATA
Fibre Channel 1
4 Gig Fibre Channel
10 Gig Fibre Channel
12 Gig Ethernet
HDTV
T
ABLE
3A. C
OMMON
C
ONFIGURATIONS
T
ABLE
Input
Reference Clock
27
22.4
24.75
25
14.8351649
19.44
19.44
19.44
19.44
19.53125
20
25
25
25
25
25
26.5625
26.5625
26.5625
31.25
M Divider Value
22
25
24
24
40
32
32
32
32
32
25
25
25
24
24
24
24
24
24
18
N Divider Value
8
8
8
3
8
4
8
1
2
4
2
5
10
6
4
8
6
3
4
3
VCO (MHz)
594
560
59 4
600
593.4066
622.08
622.08
622.08
622.08
625
50 0
625
625
600
60 0
60 0
637.5
637.5
637.5
562.5
Application
HDTV
T
ABLE
3B. P
ROGRAMMABLE
M O
UTPUT
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
M2
0
0
0
0
1
1
M1
0
0
1
1
0
0
M0
0
1
0
1
0
1
M Divider
Value
18
22
24
25
32
40
Input Frequency (MHz)
Minimum
27.22
22.27
20.41
19.6
15.31
12.25
Maximum
35.56
29.09
26.67
25.6
20
16
T
ABLE
3C. P
ROGRAMMABLE
N O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N2
0
0
0
0
1
1
1
1
N1
0
0
1
1
0
0
1
1
N0
0
1
0
1
0
1
0
1
M Divide Value
1
2
3
4
5
6
8
10
T
ABLE
3D. B
YPASS
M
ODE
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
843001AG-22
SEL0
0
1
0
1
Reference
XTAL0
XTAL1
TEST_CLK
TEST_CLK
PLL Mode
Active
Active
Active
Bypass
www.icst.com/products/hiperclocks.html
3
REV. A JUNE 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001-22
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-0.5V to V
CCO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Outputs, V
O
(LVCMOS)
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_PECL
= V
CCO_CMOS
= 3.3V±10%, TA = 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO_PECL
,
V
CCO_CMOS
I
EE
I
CCO_PECL
,
I
CCO_CMOS
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.97
2.97
2.97
Typical
3.3
3.3
3.3
115
5
Maximum
3.63
3.63
3.63
Units
V
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_CMOS
= 3.3V±10%, TA = 0°C
TO
70°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
SEL0, SEL1, MR, M0:M2,
N0:N2, TEST_CLK
OE
SEL0, SEL1, MR, M0:M2,
N0:N2, TEST_CLK
OE
TEST_CLK, SEL0, SEL1,
MR, M0, M1, N2, OE
M2, N0, N1
TEST_CLK, SEL0, SEL1,
MR, M0, M1, N2, OE
M2, N0, N1
Test Conditions
Minimum Typical
2
V
CC
- 0.4
-0.3
0.8
V
CC
+ 0.3
V
CC
= V
IN
= 3.63V
V
CC
= V
IN
= 3.63V
V
CC
= 3.63V, V
IN
= 0V
V
CC
= 3.63V, V
IN
= 0V
-5
-150
2.6
0.5
150
5
Maximum
V
CC
+ 0.3
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
IL
I
IH
I
IL
V
OH
Output High Voltage; NOTE 1
Output Low Voltage: Note 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_CMOS
/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit Diagram".
843001AG-22
www.icst.com/products/hiperclocks.html
4
REV. A JUNE 17, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843001-22
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
0.6
Typical
Maximum
V
CCO
- 0.9
V
CCO
- 1.7
1.0
Units
V
V
V
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_PECL
= 3.3V±10%, TA = 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_PECL
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
12
Test Conditions
Minimum
Typical
Maximum
40
50
7
1
Units
MH z
MHz
Ω
pF
mW
Fundamental
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO_PECL
= V
CCO_CMOS
= 3.3V±10%, TA = 0°C
TO
70°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter, (Random);
NOTE 1, 2
PLL VCO Lock Range
Output Rise/Fall Time
Test Conditions
622.08MHz,
Integration Range: 1kHz - 20MHz
490
20% to 80%
450
50
Minimum
49
0.79
640
Typical
Maximum
640
Units
MHz
ps
MH z
ps
%
t
jit(Ø)
f
VCO
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Phase jitter using a crystal interface.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
843001AG-22
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 17, 2005
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