HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
◆
70T633/1S
Features
◆
◆
◆
◆
◆
◆
◆
Functional Block Diagram
UB
L
LB
L
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
Full hardware support of semaphore signaling between
ports on-chip
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array and 208-ball fine pitch
Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
UB
R
LB
R
R/
W
L
B
E
0
L
B
E
1
L
B
E
1
R
B
E
0
R
R/
W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
512/256K x 18
MEMORY
ARRAY
I/O
0L
- I/O
17L
Din_L
Din_R
I/O
0R
- I/O
17R
A
18L
(1)
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
18R
(1)
A
0R
TDI
OE
L
CE
0L
CE
1L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
CE
0R
CE
1R
TDO
JTAG
TCK
TMS
TRST
R/W
L
R/W
R
BUSY
L(2,3)
SEM
L
INT
L(3)
(4)
(4)
ZZ
L
ZZ
R
NOTES:
CONTROL
LOGIC
1. Address A
18
x is a NC for IDT70T631.
2.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
3
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,
INTx,
M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
BUSY
R(2,3)
M/S
SEM
R
INT
R(3)
ZZ
5670 drw 01
AUGUST 2019
DSC-5670/11
1
©2019 Integrated Device Technology, Inc.
70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous
Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-
TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either
CE
0
or CE
1
) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The IDT70T633/1 has a RapidWrite Mode which allows the designer
to perform back-to-back write operations without pulsing the R/W input
each cycle. This is especially significant at the 10ns cycle times of the
IDT70T633/1, easing design considerations at these high performance
levels.
The 70T633/1 can support an operating voltage of either 3.3V or 2.5V
on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (V
DD
) remains at 2.5V.
2
70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(1,2,3)
70T633/1
BC256
(5,6)
BCG256
(5,6)
256-Pin BGA
Top View
A1
A2
A3
A4
A6
A7
A8
A9
A11
A12
A13
A14
A5
A10
A15
A16
NC
B1
TDI
B2
NC
B3
A
17L
B4
A
14L
B5
A
11L
B6
A
8L
B7
NC
B8
CE
1L
B9
OE
L
B10
INT
L
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
NC
C1
NC
C2
TDO A
18L
(4)
A
15L
C3
C4
C5
A
12L
C6
A
9L
C7
UB
L
C8
CE
0L
R/W
L
C9
C10
NC
C11
A
4L
C12
A
1L
C13
NC
C14
NC
C15
NC
C16
NC
D1
I/O
9L
D2
V
SS
D3
A
16L
D4
A
13L
D5
A
10L
D6
A
7L
D7
NC
D8
LB
L
D9
SEM
L
BUSY
L
D10
D11
A
6L
D12
A
3L
D13
OPT
L
D14
NC
D15
I/O
8L
D16
NC
E1
I/O
9R
E2
NC
E3
V
DD
E4
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
E5
E6
E7
E8
E9
E10
E11
E12
E13
NC
E14
NC
E15
I/O
8R
E16
I/O
10R
I/O
10L
F1
F2
NC
F3
V
DDQL
F4
V
DD
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
F12
F13
NC
F14
I/O
7L
I/O
7R
F15
F16
I/O
11L
G1
NC
G2
I/O
11R
V
DDQL
V
DD
G3
G4
G5
NC
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
G12
V
DDQR
I/O
6R
G13
G14
NC
G15
I/O
6L
G16
NC
H1
NC
H2
I/O
12L
V
DDQR
H3
H4
V
SS
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
H13
I/O
5L
H14
NC
H15
NC
H16
NC
J1
I/O
12R
J2
NC
J3
V
DDQR
V
SS
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
J13
NC
J14
NC
J15
I/O
5R
J16
I/O
13L
I/O
14R
I/O
13R
V
DDQL
ZZ
R
K1
K2
K3
K4
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
ZZ
L
K12
V
DDQR
I/O
4R
I/O
3R
I/O
4L
K13
K14
K15
K16
NC
L1
NC
L2
I/O
14L
V
DDQL
L3
L4
V
SS
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
NC
L13
L14
NC
L15
I/O
3L
L16
I/O
15L
M1
NC
M2
I/O
15R
V
DDQR
V
DD
M3
M4
M5
NC
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
2L
M13
M14
NC
M15
I/O
2R
M16
I/O
16R
I/O
16L
N1
N2
NC
N3
V
DDQR
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
N12
V
DDQL
I/O
1R
N13
N14
I/O
1L
N15
NC
N16
NC
P1
I/O
17R
P2
NC
P3
V
DD
V
DDQR
V
DDQR
V
DDQL
P4
P5
P6
P7
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P8
P9
P10
P11
P12
V
DD
P13
NC
P14
I/O
0R
P15
NC
P16
NC
R1
I/O
17L
TMS
R2
R3
A
16R
R4
A
13R
R5
A
10R
R6
A
7R
R7
NC
R8
LB
R
SEM
R
BUSY
R
R9
R10
R11
A
6R
R12
A
3R
R13
NC
R14
NC
R15
I/O
0L
R16
NC
T1
NC
T2
TRST
A
18R
(4)
A
15R
T3
T4
T5
A
12R
T6
A
9R
T7
UB
R
T8
CE
0R
R/W
R
T9
T10
M/S
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
NC
A
17R
A
14R
A
11R
A
8R
NC
CE
1R
OE
R
INT
R
A
5R
A
2R
A
0R
NC
NC
5670 drw 02c
NOTES:
1. All V
DD
pins must be connected to 2.5V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
3. All V
SS
pins must be connected to ground supply.
4. A
18X
is a NC for IDT70T631.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
,
3
70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
2
NC
3
V
SS
4
TDO
5
NC
6
A
16L
7
A
12L
8
A
8L
9
NC
10 11
V
DD
SEM
L
12
INT
L
13 14
A
4L
A
0L
15
OPT
L
16 17
NC
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
V
SS
NC
TDI
A
17L
A
13L
A
9L
NC
CE
0L
V
SS
BUSY
L
A
5L
A
1L
V
SS
V
DDQR
I/O
8L
NC
V
DDQL
I/O
9R
V
DDQR
V
DD
A
18L
(4)
A
14L
A
10L
UB
L
CE
1L
V
SS
R/W
L
A
6L
A
2L
V
DD
I/O
8R
NC
V
SS
NC
V
SS
I/O
10L
NC
A
15L
A
11L
A
7L
LB
L
V
DD
OE
L
NC
A
3L
V
DD
NC
V
DDQL
I/O
7L
I/O
7R
I/O
11L
NC
V
DDQR
I/O
10R
I/O
6L
NC
V
SS
NC
V
DDQL
I/O
11R
NC
V
SS
V
SS
I/O
6R
NC
V
DDQR
NC
V
SS
I/O
12L
NC
NC
V
DDQL
I/O
5L
NC
V
DD
NC
V
DDQR
I/O
12R
70T633/1
BF208
(5,6)
BFG208
(5,6)
208-Ball BGA
Top View
(7)
V
DD
NC
V
SS
I/O
5R
V
DDQL
V
DD
V
SS
ZZ
R
ZZ
L
V
DD
V
SS
V
DDQR
I/O
14R
V
SS
I/O
13R
V
SS
I/O
3R
V
DDQL
I/O
4R
V
SS
NC
I/O
14L
V
DDQR
I/O
13L
NC
I/O
3L
V
SS
I/O
4L
V
DDQL
NC
I/O
15R
V
SS
V
SS
NC
I/O
2R
V
DDQR
NC
V
SS
NC
I/O
15L
I/O
1R
V
DDQL
NC
I/O
2L
I/O
16R
I/O
16L
V
DDQR
NC
TRST
A
16R
A
12R
A
8R
NC
V
DD
SEM
R
INT
R
A
4R
NC
I/O
1L
V
SS
NC
V
SS
NC
I/O
17R
TCK
A
17R
A
13R
A
9R
NC
CE
0R
V
SS
BUSY
R
A
5R
A
1R
V
SS
V
DDQL
I/O
0R
V
DDQR
NC
I/O
17L
V
DDQL
TMS
A
18R
(4)
A
14R
A
10R
UB
R
CE
1R
V
SS
R/W
R
A
6R
A
2R
V
SS
NC
V
SS
NC
V
SS
NC
V
DD
NC
A
15R
A
11R
A
7R
LB
R
V
DD
OE
R
M/S
A
3R
A
0R
V
DD
OPT
R
NC
I/O
0L
5670 drw 02b
NOTES:
1. All V
DD
pins must be connected to 2.5V power supply.
2. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(2.5V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
3. All V
SS
pins must be connected to ground.
4. A
18X
is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
4
70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
CE
0L
,
CE
1L
R/W
L
OE
L
A
0L
- A
18L
(1)
I/O
0L
- I/O
17L
SEM
L
INT
L
BUSY
L
UB
L
LB
L
V
DDQL
OPT
L
ZZ
L
M/S
V
DD
V
SS
TDI
TDO
TCK
TMS
TRST
Right Port
CE
0R
,
CE
1R
R/W
R
OE
R
A
0R
- A
18R
(1)
I/O
0R
- I/O
17R
SEM
R
INT
R
BUSY
R
UB
R
LB
R
V
DDQR
OPT
R
ZZ
R
Names
Chip Enables (Input)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Semaphore Enable (Input)
Interrupt Flag (Output)
Busy Flag (Output)
Upper Byte Select (Input)
Lower Byte Select (Input)
Power (I/O Bus) (3.3V or 2.5V)
(2)
(Input)
Option for selecting V
DDQX
(2,3)
(Input)
Sleep Mode Pin
(4)
(Input)
Master or Slave Select (Input)
(5)
Power (2.5V)
(2)
(Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
5670 tbl 01
NOTES:
1. Address A
18
x is a NC for IDT70T631.
2. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on I/O
X
.
3. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to V
DD
(2.5V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to V
SS
(0V), then that
port's I/Os and controls will operate at 2.5V levels and V
DDQX
must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. OPTx,
INTx,
M/S and the sleep mode pins themselves (ZZx) are
not affected during sleep mode. It is recommended that boundary scan not be
operated during sleep mode.
5.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master
(M/S=V
IH
).
5
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