• Function and pinout compatible with FCT, and F logic
• FCT-C speed at 4.2 ns max. (Com’l),
FCT-A speed at 5.2 ns max. (Com’l)
• Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Extended commercial range of
−40°C
to +85°C
• Fully compatible with TTL input and output logic levels
• Sink current
64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT373T and FCT573T consist of eight latches with
three-state outputs for bus organized applications. When latch
enable (LE) is HIGH, the flip-flops appear transparent to the
data. Data that meets the required set-up times are latched
when LE transitions from HIGH to LOW. Data appears on the
bus when the (OE) is LOW. When output enable is HIGH, the
bus output is in the impedance state. In this mode, data may
be entered into the latches. The FCT573T is identical to the
FCT373T except for the flow-through pinout, which simplifies
board design.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
D
0
LE
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
CP
D
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations
DIP/SOIC/QSOP
Top View
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
6
7
8
9
10
20
19
18
17
15
14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
DIP/SOIC/QSOP
Top View
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
FCT373T
5
16
FCT573T
Logic Symbol
D
0
LE
OE
O
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
May 1994 – Revised March 18, 1997
CY54/74FCT373T
CY54/74FCT573T
Function Table
[1]
Inputs
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
Outputs
O
H
L
Q
0
Z
Supply Voltage to Ground Potential ...............–0.5V to +7.0V
DC Input Voltage ............................................–0.5V to +7.0V
DC Output Voltage .........................................–0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ...... 120 mA
Power Dissipation.......................................................... 0.5W
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
[2, 3]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –65°C to +135°C
Operating Range
Range
Commercial
Commercial
Military
[4]
Range
DT
T, AT, CT
All
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
V
CC
5V
±
5%
5V
±
5%
5V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Output HIGH Voltage
Test Conditions
V
CC
=Min., I
OH
=–32 mA
V
CC
=Min., I
OH
=–15 mA
V
CC
=Min., I
OH
=–12 mA
V
OL
V
IH
V
IL
V
H
V
IK
I
I
I
IH
I
IL
I
OZH
I
OZL
I
OS
I
OFF
Output LOW Voltage
V
CC
=Min., I
OL
=64 mA
V
CC
=Min., I
OL
=32 mA
Input HIGH Voltage
Input LOW Voltage
Hysteresis
[6]
Input Clamp Diode Voltage
Input HIGH Current
Input HIGH Current
Input LOW Current
Off State HIGH-Level Output
Current
Off State LOW-Level
Output Current
Output Short Circuit Current
[7]
Power-Off Disable
All inputs
V
CC
=Min., I
IN
=–18 mA
V
CC
=Max., V
IN
=V
CC
V
CC
=Max., V
IN
=2.7V
V
CC
=Max., V
IN
=0.5V
V
CC
=Max., V
OUT
=2.7V
V
CC
=Max., V
OUT
=0.5V
V
CC
=Max., V
OUT=
0.0V
V
CC
=0V, V
OUT
=4.5V
–60
–120
0.2
–0.7
–1.2
5
±1
±1
10
–10
–225
±1
Com’l
Com’l
Mil
Com’l
Mil
2.0
0.8
Min.
2.0
2.4
2.4
3.3
3.3
0.3
0.3
0.55
0.55
Typ.
[5]
Max.
Unit
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
mA
µA
Notes:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = HIGH Impedance
Q
n
= Previous state of flip flops (Q
n-1
)
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
CC
or ground.
4. T
A
is the “instant on” case temperature.
5. Typical values are at V
CC
=5.0V, T
A
=+25°C ambient.
6. This parameter is guaranteed but not tested.
7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
OS
tests should be performed last.
2
CY54/74FCT373T
CY54/74FCT573T
Capacitance
[6]
Parameter
C
IN
C
OUT
Input Capacitance
Output Capacitance
Description
Typ.
[5]
6
8
Max.
10
12
Unit
pF
pF
Power Supply Characteristics
Parameter
I
CC
∆I
CC
I
CCD
Description
Quiescent Power Supply Current
Quiescent Power Supply Current
(TTL inputs HIGH)
Dynamic Power Supply Current
[9]
Test Conditions
V
CC
=Max., V
IN
≤
0.2V, V
IN
≥
V
CC
– 0.2V
V
CC
=Max., V
IN
=3.4V, f
1
=0, Outputs Open
[8]
V
CC
=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
OE=GND, V
IN
≤
0.2V or V
IN
≥
V
CC
– 0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE=GND, LE=V
CC
V
IN
≤
0.2V or V
IN
≥
V
CC
– 0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
1
=10 MHz,
OE=GND, LE=V
CC
, V
IN
=3.4V or V
IN
=GND
V
CC
=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, LE=V
CC
,
V
IN
≤
0.2V or V
IN
≥
V
CC
– 0.2V
V
CC
=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
1
=2.5 MHz,
OE=GND, LE=V
CC
V
IN
=3.4V or V
IN
=GND
Notes:
8. Per TTL driven input (V
IN
=3.4V); all other inputs at V
CC
or GND.
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
10. I
C
I
C
= I
CC
+∆I
CC
D
H
N
T
+I
CCD
(f
0
/2 + f
1
N
1
)
I
CC
= Quiescent Current with CMOS input levels
∆I
CC
= Power Supply Current for a TTL HIGH input (V
IN
=3.4V)
D
H
= Duty Cycle for TTL inputs HIGH
N
T
= Number of TTL inputs at D
H
I
CCD
= Dynamic Current caused by an input transition pair (HLH or LHL)
f
0
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
f
1
= Number of inputs changing at f
1
N
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
Typ.
[5]
0.1
0.5
0.6
Max.
0.2
2.0
0.12
Unit
mA
mA
mA/MHz
I
C
Total Power Supply Current
[10]
0.7
1.4
mA
1.0
2.4
mA
1.3
2.6
[11]
mA
3.3
10.6
[11]
mA
3
CY54/74FCT373T
CY54/74FCT573T
e
Switching Characteristics
Over the Operating Range
[12]
FCT373T/FCT573T
Military
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
Description
Propagation Delay
D to O
Propagation Delay
LE to O
Output Enable Time
Output Disable Time
Set-Up Time
HIGH to LOW
D to LE
Set-Up Time
HIGH to LOW
D to LE
LE Pulse
Width HIGH
Min.
1.5
2.0
1.5
1.5
2.0
Max.
8.5
15.0
13.5
10.0
Commercial
Min.
1.5
2.0
1.5
1.5
2.0
Max.
8.0
13.0
12.0
7.5
Min.
1.5
2.0
1.5
1.5
2.0
FCT373AT/FCT573AT
Military
Max.
5.6
9.8
7.5
6.5
Commercial
Min.
1.5
2.0
1.5
1.5
2.0
Max.
5.2
8.5
6.5
5.5
Unit
ns
ns
ns
ns
ns
Fig.
No.
[13]
1, 3
1, 5
1, 7, 8
1, 7, 8
9
t
H
1.5
1.5
1.5
1.5
ns
9
t
W
6.0
6.0
6.0
5.0
ns
5
FCT373CT/
FCT573CT
Commercial
Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
t
H
t
W
Description
Propagation Delay D to O
Propagation Delay LE to O
Output Enable Time
Output Disable Time
Set-Up Time, HIGH to LOW D to LE
Set-Up Time, HIGH to LOW D to LE
LE Pulse Width HIGH
Min.
1.5
2.0
1.5
1.5
2.0
1.5
5.0
Max.
4.2
5.5
5.5
5.0
FCT373DT/
FCT573DT
Commercial
Min.
1.5
2.0
1.5
1.5
1.5
1.0
3.0
Max.
3.8
4.0
4.8
4.0
Unit
ns
ns
ns
ns
ns
ns
ns
Fig. No.
[13]
1, 3
1, 5
1, 7, 8
1, 7, 8
9
9
5
Shaded areas contain preliminary information.
Note:
12. Minimum limits are guaranteed but not tested on Propagation Delays.
13. See “Parameter Measurement Information” in the General Information section.
工作这点儿事
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
