74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
Rev. 3 — 16 August 2013
Product data sheet
1. General description
The 74AVC16374 is a 16-bit edge triggered flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. The 74AVC16374 consist
of 2 sections of 8 edge-triggered flip-flops. A clock input (CP) and an output enable (OE)
are provided per 8-bit section.
The 74AVC16374 is designed to have an extremely fast propagation delay and a
minimum amount of power consumption.
To ensure the high-impedance output state during power-up or power-down, nOE should
be tied to VCC through a pull-up resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line
drive during transient (see
Figure 5
and
Figure 6).
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance,
resulting in noise reduction without speed degradation
Low inductance multiple V
CC
and GND pins to minimize noise and ground bounce
Supports Live Insertion
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AVC16374DGG
40 C
to +85
C
Name
TSSOP48
Description
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT362-1
Type number
Nexperia
74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
4. Functional diagram
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mna577
1OE
1CP
2OE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1EN
C1
2EN
C2
1D
1
2
3
5
6
8
9
11
12
2D
2
13
14
16
17
19
20
22
23
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1OE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1CP
48
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2CP
25
mna576
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
Fig 1.
IEC logic symbol
Fig 2.
Logic symbol
1D0
D
CP
Q
1Q0
1CP
FF1
1OE
to 7 other channels
2D0
D
CP
Q
2Q0
2CP
FF9
2OE
to 7 other channels
mna578
Fig 3.
Logic diagram
74AVC16374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 August 2013
2 of 16
Nexperia
74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
5. Pinning information
5.1 Pinning
74AVC16374
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1CP
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2CP
mna575
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Fig 4.
Pin configuration
74AVC16374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 August 2013
3 of 16
Nexperia
74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
5.2 Pin description
Table 2.
Symbol
1OE
1Q0 to 1Q7
GND
V
CC
2Q0 to 2Q7
2OE
2CP
2D0 to 2D7
1D0 to 1D7
1CP
Pin description
Pin
1
2, 3, 5, 6, 8, 9, 11, 12
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
13, 14, 16, 17, 19, 20, 22, 23
24
25
36, 35, 33, 32, 30, 29, 27, 26
47, 46, 44, 43, 41, 40, 38, 37
48
Description
output enable input (active LOW)
3-state flip-flop outputs
ground (0 V)
supply voltage
3-state flip-flop outputs
output enable input (active LOW)
clock input
data input/output
data input/output
clock input
6. Functional description
Table 3.
Function table
[1]
Inputs
nOE
Load and read register
Load register and disable outputs
L
L
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH CP transition
Operating modes
Internal flip-flops
nCp
nDn
I
h
I
h
L
H
L
H
Outputs
nQn
L
H
Z
Z
74AVC16374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 August 2013
4 of 16
Nexperia
74AVC16374
16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
0.5
50
[1]
[1]
Max
+4.6
50
+4.6
-
V
CC
+ 0.5
+4.6
50
+100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
< 0 V
output HIGH or LOW
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +85
C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Above 60
C,
the value of P
tot
derates linearly with 5.5 mW/K.
8. Recommended operating conditions
Table 5.
V
CC
Recommended operating conditions
Conditions
according to JEDEC Low Voltage Standards
Min
1.4
1.65
2.3
3.0
for low-voltage applications
V
I
V
O
T
amb
t/V
input voltage
output voltage
ambient temperature
input transition rise and fall
rate
output HIGH or LOW
output 3-state
in free air
V
CC
= 1.4 V to 1.6 V
V
CC
= 1.65 V to 2.3 V
V
CC
= 2.3 V to 3.0 V
V
CC
= 3.0 V to 3.6 V
1.2
0
0
0
40
0
0
0
0
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
1.6
1.95
2.7
3.6
3.6
3.6
V
CC
3.6
+85
40
30
20
10
Unit
V
V
V
V
V
V
V
V
C
ns/V
ns/V
ns/V
ns/V
supply voltage
Symbol Parameter
74AVC16374
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 16 August 2013
5 of 16
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