74ALVT16373
Rev. 4 — 2 February 2018
16-bit transparent D-type latch; 3-state
Product data sheet
1
General description
The 74ALVT16373 is a high-performance BiCMOS product designed for V
CC
operation at
2.5 V or 3.3 V with I/O compatibility up to 5 V.
This device is a 16-bit transparent D-type latch with non-inverting 3-state bus compatible
outputs. The device can be used as two 8-bit latches or one 16-bit latch. When latch
enable (nLE) input is HIGH, the nQn outputs follow the date (nDn) inputs. When latch
enable is taken LOW, the nQn outputs are latched at the levels of the D inputs one setup
time prior to the HIGH-to-LOW transition.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit transparent latch
5 V I/O compatible
3-state buffers
Output capability: +64 mA/–32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-State
No bus current loading when output is tied to 5 V bus
Latch-up protection:
–
JESD 17: exceeds 500 mA
ESD protection:
–
MIL STD 883 method 3015: exceeds 2000 V
–
MM exceeds 200 V
3
Ordering information
Package
Temperature range Name
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
-40 °C to +85 °C
-40 °C to +85 °C
SSOP48
TSSOP48
Table 1. Ordering information
Type number
74ALVT16373DL
74ALVT16373DGG
Nexperia
16-bit transparent D-type latch; 3-state
74ALVT16373
4
Functional diagram
1
1OE
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1LE
48
2LE
25
mgu768
24
2OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1OE
1LE
2OE
2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
1
2
3
5
6
8
9
11
12
4D
2
13
14
16
17
19
20
22
23
mgu770
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
Figure 1. Logic symbol
1D0
D
Q
1Q0
Figure 2. IEC logic symbol
2D0
D
Q
2Q0
LATCH
1
LE
LE
LATCH
9
LE
LE
1LE
1OE
to 7 other channels
2LE
2OE
to 7 other channels
mgu769
Figure 3. Logic diagram
74ALVT16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 2 February 2018
2 / 16
Nexperia
16-bit transparent D-type latch; 3-state
74ALVT16373
5
Pinning information
5.1 Pinning
74ALVT16373
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
1
2
3
4
5
6
7
8
9
48 1LE
47 1D0
46 1D1
45 GND
44 1D2
43 1D3
42 V
CC
41 1D4
40 1D5
39 GND
38 1D6
37 1D7
36 2D0
35 2D1
34 GND
33 2D2
32 2D3
31 V
CC
30 2D4
29 2D5
28 GND
27 2D6
26 2D7
25 2LE
aaa-028126
GND 10
1Q6 11
1Q7 12
2Q0 13
2Q1 14
GND 15
2Q2 16
2Q3 17
V
CC
18
2Q4 19
2Q5 20
GND 21
2Q6 22
2Q7 23
2OE 24
Figure 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7
2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7
1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7
2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7
1OE, 2OE
1LE, 2LE
GND
V
CC
Pin
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
1, 24
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
Description
data inputs
data inputs
data outputs
data outputs
output enable inputs (active LOW)
latch enable inputs (active HIGH)
ground (0 V)
supply voltage
74ALVT16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 2 February 2018
3 / 16
Nexperia
16-bit transparent D-type latch; 3-state
74ALVT16373
6
Functional description
[1]
Table 3. Function table
Operating mode
Inputs
nOE
nLE
H
H
↓
↓
L
L
H
nDn
L
H
l
h
X
X
nDn
L
L
L
L
L
H
H
Internal
latches
L
H
L
H
NC
NC
nDn
Outputs
nQn
L
H
L
H
NC
Z
Z
enable and read register (transparent mode)
latch and read register
Hold
Latch register and disable outputs
[1] H = HIGH voltage level;
L = LOW voltage level;
↓ = HIGH-to-LOW LE transition;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
NC = No change;
Z = high-impedance OFF-state.
7
Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
j
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
storage temperature
junction temperature
[2]
[1]
Conditions
Min
-0.5
-0.5
-0.5
-50
-50
-
-64
-65
-
Max
+4.6
+7.0
+7.0
-
-
128
-
+150
+150
Unit
V
V
V
mA
mA
mA
mA
°C
°C
output in OFF-state or HIGH-state
V
I
< 0 V
V
O
< 0 V
output in LOW-state
output in HIGH-state
[1]
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are
detrimental to reliability.
74ALVT16373
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 2 February 2018
4 / 16
Nexperia
16-bit transparent D-type latch; 3-state
74ALVT16373
8
Recommended operating conditions
Parameter
supply voltage
input voltage
HIGH-level output current
LOW-level output current
none
current duty cycle ≤ 50 %;
f
i
≥ 1 kHz
Conditions
V
CC
= 2.5 V ± 0.2 V
Min
Max
2.7
5.5
-8
8
24
10
+85
2.3
0
-
-
-
-
-40
V
CC
= 3.3 V ± 0.3 V
Min
3.0
0
-
-
-
-
-40
Max
3.6
5.5
-32
32
64
10
+85
V
V
mA
mA
mA
ns/V
°C
Unit
Table 5. Recommended operating conditions
Symbol
V
CC
V
I
I
OH
I
OL
Δt/ΔV
T
amb
input transition rise
and fall rate
ambient temperature
outputs enabled
free-air
9
Static characteristics
Table 6. Static characteristics
At recommended operating conditions; T
amb
= -40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
V
OL(pu)
I
I
Parameter
input clamping voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
V
CC
= 2.3 V to 2.7 V; I
O
= -100 μA
V
CC
= 2.3 V; I
O
= -8 mA
V
CC
= 2.3 V; I
O
= 100 μA
V
CC
= 2.3 V; I
O
= 24 mA
power-up LOW-level output V
CC
= 2.7 V; I
O
= 1 mA;
voltage
V
I
= V
CC
or GND
input leakage current
all input pins
V
CC
= 0 V or 2.7 V; V
I
= 5.5 V
control pins
V
CC
= 2.7 V; V
I
= V
CC
or GND
data pins;
V
CC
= 2.7 V; V
I
= V
CC
V
CC
= 2.7 V; V
I
= 0 V
I
OFF
I
BHL
I
BHH
I
EX
74ALVT16373
Conditions
V
CC
= 2.3 V; I
IK
= -18 mA
Min
-
1.7
-
V
CC
- 0.2
1.8
-
-
[2]
Typ
[1]
Max
-1.2
-
0.7
-
-
0.2
0.5
0.55
Unit
V
V
V
V
V
V
V
V
V
CC
= 2.5 V ± 0.2 V
-0.85
-
-
-
-
0.07
0.3
-
-
[3]
-
-
[3]
0.1
0.1
0.1
0.1
0.1
90
-10
10
10
±1
1
-5
±100
-
-
125
μA
μA
μA
μA
μA
μA
μA
μA
-
-
-
[4]
[4]
power-off leakage current
bus hold LOW current
bus hold HIGH current
external current
V
CC
= 0 V; V
I
or V
O
= 0 V to 4.5 V
data inputs; V
CC
= 2.3 V; V
I
= 0.7 V
data inputs; V
CC
= 2.3 V; V
I
= 1.7 V
output in HIGH-state when V
O
> V
CC
;
V
O
= 5.5 V; V
CC
= 2.3 V
All information provided in this document is subject to legal disclaimers.
-
-
-
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 4 — 2 February 2018
5 / 16
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