FINAL
COM’L: H-5/7/10/15/25, Q-10/15/25
IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s
Pin and function compatible with all GAL
s
s
Advanced
Micro
Devices
s
Peripheral Component Interconnect (PCI)
s
s
s
s
s
s
s
s
s
s
20V8/As
Electrically erasable CMOS technology pro-
vides reconfigurable logic and full testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for a wide range of
24-pin PAL devices
Programmable enable/disable control
Outputs individually programmable as
registered or combinatorial
compliant
Preloadable output registers for testability
Automatic register reset on power-up
Cost-effective 24-pin plastic SKINNYDIP and
28-pin PLCC packages
Extensive third-party software and programmer
support through FusionPLD partners
Fully tested for 100% programming and func-
tional yields and high reliability
Programmable output polarity
5-ns version utilizes a split leadframe for
improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with
low-power, high-speed, electrically-erasable CMOS
technology. Its macrocells provide a universal device
architecture. The PALCE20V8 is fully compatible with
the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the
user’s design specification. A design is implemented
using any of a number of popular design software pack-
ages, allowing automatic creation of a programming file
based on Boolean or state equations. Design software
also verifies the design and can provide test vectors for
the finished device. Programming can be accomplished
on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products
(AND/OR) architecture that allows users to implement
complex logic functions easily and efficiently. Multiple
levels of combinatorial logic can always be reduced to
sum-of-products form, taking advantage of the very
wide input gates available in PAL devices. The equa-
tions are programmed into the device through floating-
gate cells in the AND logic array that can be erased
electrically.
The fixed OR array allows up to eight data product terms
per output for logic functions. The sum of these products
feeds the output macrocell. Each macrocell can be
programmed as registered or combinatorial with an
active-high or active-low output. The output configura-
tion is determined by two global bits and one local bit
controlling four multiplexers in each macrocell.
BLOCK DIAGRAM
10
I
1
– I
10
CLK/I
0
Programmable AND Array
40 x 64
Input
Mux.
MACRO
MC
0
MACRO
MC
1
MACRO
MC
2
MACRO
MC
3
MACRO
MC
4
MACRO
MC
5
MACRO
MC
6
MACRO
MC
7
Input
Mux.
OE/I
11
I
12
Publication#
16491
Rev.
D
Issue Date:
February 1996
I/O
0
I/O
1
I/O
2
I/O
4
I/O
4
I/O
5
I/O
6
I/O
7
I
13
16491D-1
Amendment
/0
2-155
AMD
CONNECTION DIAGRAMS
(Top View)
SKINNYDIP
CLK/I
0
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
I
10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
13
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
I
12
OE/I
11
16491D-2
PLCC/LCC
CLK/I0
NC
VCC
I/O7
25
24
23
22
21
20
19
12 13 14 15 16 17 18
GND
NC
OE/I
11
I12
I10
I9
I/O0
16491D-3
4
I3
I4
I5
NC
I6
I7
I8
5
6
7
8
9
10
11
3 2 1 28 27 26
I/O6
I/O5
I/O4
NC
I/O3
I/O2
I/O1
Note:
Pin 1 is marked for orientation.
PIN DESIGNATIONS
CLK
GND
I
I/O
NC
OE
V
CC
= Clock
= Ground
= Input
= Input/Output
= No Connect
= Output Enable
= Supply Voltage
2-156
PALCE20V8 Family
I13
I2
I1
AMD
ORDERING INFORMATION
Commercial and Industrial Products
AMD programmable logic products for commercial and industrial applications are available with several ordering options. The
order number (Valid Combination) is formed by a combination of:
PAL
FAMILY TYPE
PAL = Programmable Array Logic
TECHNOLOGY
CE = CMOS Electrically Erasable
NUMBER OF ARRAY INPUTS
OUTPUT TYPE
V = Versatile
NUMBER OF FLIP-FLOPS
POWER
H = Half Power (90-125 mA I
CC
)
Q = Quarter Power (55 mA I
CC
)
SPEED
-5 = 5 ns t
PD
-7 = 7.5 ns t
PD
-10 = 10 ns t
PD
-15 = 15 ns t
PD
-20 = 20 ns t
PD
-25 = 25 ns t
PD
CE
20 V 8 H -5 P C /5
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/4
= First Revision
/5
Second Revision
(Same algorithm as /4)
OPERATING CONDITIONS
C = Commercial (0
°
C to +75
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
P = 24-Pin 300 mil Plastic
SKINNYDIP (PD3024)
J = 28-Pin Plastic Leaded Chip
Carrier (PL 028)
Valid Combinations
PALCE20V8H-5
JC
/5
PALCE20V8H-7
Blank, /4
PALCE20V8H-10
PC, JC
/5
PALCE20V8Q-10
PALCE20V8H-15
PC, JC, PI, JI
PALCE20V8Q-15
PC, JC
Blank,
/4
PALCE20V8Q-20
PI, JI
PALCE20V8H-25
PC, JC, PI, JI
PALCE20V8Q-25
Valid Combinations
Valid Combinations lists configurations planned to
be supported in volume for this device. Consult the
local AMD sales office to confirm availability of spe-
cific valid combinations and to check on newly re-
leased combinations.
PALCE20V8H-5/7/10/15/25, Q-10/15/25 (Com’l)
PALCE20V8H-15/25, Q-20/25 (Ind)
2-157
AMD
FUNCTIONAL DESCRIPTION
The PALCE20V8 is a universal PAL device. It has eight
independently configurable macrocells (MC
0
..MC
7
).
Each macrocell can be configured as a registered out-
put, combinatorial output, combinatorial I/O, or dedi-
cated input. The programming matrix implements a
programmable AND logic array, which drives a fixed OR
logic array. Buffers for device inputs have complemen-
tary outputs to provide user-programmable input signal
polarity. Pins 1 and 13 serve either as array inputs or as
clock (CLK) and output enable (OE) for all flip-flops.
Unused input pins should be tied directly to V
CC
or GND.
Product terms with all bits unprogrammed (discon-
nected) assume the logical HIGH state and product
terms with both true and complement of any input signal
connected assume a logical LOW state.
The programmable functions on the PALCE20V8 are
automatically configured from the user’s design specifi-
cation, which can be in a number of formats. The design
specification is processed by development software to
verify the design and create a programming file. This
file, once downloaded to a programmer, configures the
device according to the user’s desired function.
The user is given two design options with the
PALCE20V8. First, it can be programmed as an emu-
lated PAL device. This includes the PAL20R8 series
and most 24-pin combinatorial PAL devices. The PAL
device programmer manufacturer will supply device
codes for the standard PAL architectures to be used
with the PALCE20V8. The programmer will program the
PALCE20V8 to the corresponding PAL device architec-
ture. This allows the user to use existing standard PAL
device JEDEC files without making any changes to
them. Alternatively, the device can be programmed
directly as a PALCE20V8. Here the user must use the
PALCE20V8 device code. This option provides full utili-
zation of the macrocells, allowing non-standard archi-
tectures to be built.
1 1
0 X
1 0
OE
V
CC
1
1
0
0
1
0
0
1
To
Adjacent
Macrocell
SL0
X
SG1
1 1
0 X
D
SL1
X
CLK
Q
Q
1 0
1 1
0 X
*SG1
SL0
X
1 0
I/O
X
From
Adjacent
Pin
16491D-4
* In Macrocells MC
0
and MC
7
,
SG1 is replaced by
SG0
on the feedback multiplexer.
Figure 1. PALCE20V8 Macrocell
2-158
PALCE20V8 Family
AMD
Configuration Options
Each macrocell can be configured as one of the follow-
ing: registered output, combinatorial output, combinato-
rial I/O or dedicated input. In the registered output
configuration, the output buffer is enabled by the
OE
pin.
In the combinatorial configuration, the buffer is either
controlled by a product term or always enabled. In the
dedicated input configuration, the buffer is always dis-
abled. A macrocell configured as a dedicated input de-
rives the input signal from an adjacent I/O.
The macrocell configurations are controlled by the con-
figuration control word. It contains 2 global bits (SG0
and SG1) and 16 local bits (SL0
0
through SL0
7
and SL1
0
through SL1
7
). SG0 determines whether registers will
be allowed. SG1 determines whether the PALCE20V8
will emulate a PAL20R8 family or a combinatorial de-
vice. Within each macrocell, SL0
x
, in conjunction with
SG1, selects the configuration of the macrocell and
SL1
x
sets the output as either active low or active high.
The configuration bits work by acting as control inputs
for the multiplexers in the macrocell. There are four mul-
tiplexers: a product term input, an enable select, an out-
put select, and a feedback select multiplexer. SG1 and
SL0
x
are the control signals for all four multiplexers. In
MC
0
and MC
7
,
SG0
replaces SG1 on the feedback
multiplexer.
These configurations are summarized in table 1 and il-
lustrated in figure 2.
If the PALCE20V8 is configured as a combinatorial de-
vice, the CLK and
OE
pins may be available as inputs to
the array. If the device is configured with registers, the
CLK and
OE
pins cannot be used as data inputs.
Dedicated Output in a Non-Registered
Device
The control settings are SG0 = 1, SG1 = 0, and SL0
x
= 0.
All eight product terms are available to the OR gate. Al-
though the macrocell is a dedicated output, the feed-
back is used, with the exception of pins 18(21) and
19(23). Pins 18(21) and 19(23) do not use feedback in
this mode.
Dedicated Input in a Non-Registered
Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0
x
=
1. The output buffer is disabled. The feedback signal is
an adjacent I/O pin.
Combinatorial I/O in a Non-Registered
Device
The control settings are SG0 = 1, SG1 = 1, and SL0
x
= 1.
Only seven product terms are available to the OR gate.
The eighth product term is used to enable the output
buffer. The signal at the I/O pin is fed back to the AND
array via the feedback multiplexer. This allows the pin to
be used as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0
x
=1.
Only seven product terms are available to the OR gate.
The eighth product term is used as the output enable.
The feedback signal is the corresponding I/O signal.
Table 1. Macrocell Configurations
SG0 SG1 SL0
x
Cell Configuration Devices Emulated
Device has registers
0
0
1
1
0
1
Registered
Output
Combinatorial I/O
PAL20R8, 20R6,
20R4
PAL20R6, 20R4
Registered Output Configuration
The control bit settings are SG0 = 0, SG1 = 1 and SL0
x
=
0. There is only one registered configuration. All eight
product terms are available as inputs to the OR gate.
Data polarity is determined by SL1
x
. SL1
x
is an input to
the exclusive-OR gate which is the D input to the flip-
flop. SL1
x
is programmed as 1 for inverted output or 0
for non-inverted output. The flip-flop is loaded on the
LOW-to-HIGH transition of CLK. The feedback path is
from
Q
on the register. The output buffer is enabled by
OE.
Device has no registers
1
1
1
0
0
1
0
1
1
Combinatorial
Output
Dedicated Input
Combinatorial I/O
PAL20L2,
18L4,16L6,14L8
PAL20L2,18L4,
16L6
PAL20L8
Combinatorial Configurations
The PALCE20V8 has three combinatorial output con-
figurations: dedicated output in a non-registered device,
I/O in a non-registered device and I/O in a registered
device.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is made through a programmable bit SL1
x
which controls an exclusive-OR gate at the output of the
AND/OR logic. The output is active high if SL1
x
is a 0
and active low if SL1
x
is a 1.
PALCE20V8 Family
2-159
FPGA/CPLD
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