ICs for Communications
Smart Integrated Digital Echo Canceller
SIDEC
PEB 20954 Version 1.1
Preliminary Product Overview Apr.1999
DS 1
PEB 20954
Revision History:
Page
Page
(in previous (in current
Version)
Version)
7
7,74
-
58,60
68,69
75
76
7
7,76
10
60,62
70,71
77,78
78
Current Version: Apr.1999, Version 1.1
Subjects (major changes since last revision)
power dissipation is 700-900 mW instead of 1200 mW
temperature range
-40°C - 85°C
instead of
0°C - 70°C
section about SIDEC in VoIP added
µP
max. timing changed from 20 ns to 25 ns
Fig. 37 and Fig. 38 interchanged (Now Fig 38 and Fig.39)
AC Characteristics added
Capacitances added
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
ABM
®
, AOP
®
, ARCOFI
®
, ARCOFI
®
-BA, ARCOFI
®
-SP, DigiTape
®
, EPIC
®
-1, EPIC
®
-S, ELIC
®
, FALC
®
54, FALC
®
56,
FALC
®
-E1, FALC
®
-LH, IDEC
®
, IOM
®
, IOM
®
-1, IOM
®
-2, IPAT
®
-2, ISAC
®
-P, ISAC
®
-S, ISAC
®
-S TE, ISAC
®
-P TE,
ITAC
®
, IWE
®
, MUSAC
®
-A, OCTAT
®
-P, QUAT
®
-S, SICAT
®
, SICOFI
®
, SICOFI
®
-2, SICOFI
®
-4, SICOFI
®
-4µC,
SLICOFI
®
are registered trademarks of Infineon Technologies AG.
ACE
™
, ASM
™
, ASP
™
, POTSWIRE
™
, QuadFALC
™
, SCOUT
™
are trademarks of Infineon Technologies AG.
Edition Apr.1999
Published by Infineon Technologies AG i. Gr.,
SC,
Balanstraße 73,
81541 München
©
Infineon Technologies AG i.Gr. 1999.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies AG is an approved CECC manufacturer.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!
Critical components
1
of the Infineon Technologies AG, may only be used in life-support devices or systems
2
with
the express written approval of the Infineon Technologies AG.
1 A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or
maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be en-
dangered.
PEB 20954
PEF 20954
1
1.1
1.2
1.3
2
2.1
2.2
3
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
3.1.11
3.1.12
3.2
3.2.1
3.2.2
3.2.3
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.8.1
4.3.8.2
4.3.9
5
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Functional Block Diagram and Description . . . . . . . . . . . . . . . . . . . . . . . . .24
Speech Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Disabling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Adaptive Echo Estimation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PCM Input/Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Non Linear Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Universal Control and Communication Interface . . . . . . . . . . . . . . . . . . .26
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
JTAG and RAM BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Description of Functional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Channelwise and Global A- and
µ-Law
Conversion . . . . . . . . . . . . . . . .27
Bypass and Disabling Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
UCC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Operational Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Pin Connection Diagram for SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Synchronization and Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Timing Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PCM Signal Timing and Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . .41
Timing of SYNCI and SYNCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Clock Timing within External VCO Capture Range . . . . . . . . . . . . . . . . .46
Serial Interface (Controlling and Monitoring) Timing . . . . . . . . . . . . . . . .47
UCC Interface Signal Timing and Frame Alignment . . . . . . . . . . . . . . . .49
Speech Highway Control Signals for CAS in T1 Systems . . . . . . . . . . . .53
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Intel Mode (IM0=’0’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Motorola Mode (IM0=’1’) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Register Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
3
04.99
Preliminary Product Overview
PEB 20954
PEF 20954
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2
6.3.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
7.1
7.2
7.3
7.4
7.5
8
9
10
SIDEC Performance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Test No.1 - Steady state residual and returned echo level test . . . . . . . . . . 70
Test No. 2 - Convergence and steady state residual and returned echo level test
72
Test 2A: Convergence test with NLP enabled . . . . . . . . . . . . . . . . . . . . . 72
Test 2B: Convergence test with NLP disabled . . . . . . . . . . . . . . . . . . . . 72
Test 2C: Convergence test in the presence of background noise . . . . . . 72
Test No. 3 - Performance under conditions of double talk . . . . . . . . . . . . . 73
Test 3A: Double talk test with low near end levels . . . . . . . . . . . . . . . . . 73
Test 3B: Double talk test with high near end levels . . . . . . . . . . . . . . . . . 73
Test 3C: Double talk under simulated conversion . . . . . . . . . . . . . . . . . . 73
Test No. 4 - Leak rate test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Infinite return loss convergence test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Non divergence on narrow band signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Stability Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Test No. 8 - Non convergence of the canceller on specific ITU-T No. 5, 6 and
7 in band signaling and continuity check tones 74
Test No. 9 - Comfort noise test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Test No. 10 - Canceller operation on the calling/caller station side . . . . . . . 75
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Package Outlines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Glossary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Index
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Preliminary Product Overview
4
04.99
PEB 20954
PEF 20954
Introduction
1
Introduction
The
Smart Integrated Digital Echo Canceller
(SIDEC) suppresses echoes in
telecommunication networks which might disturb any kind of terrestrial or wireless
communication. It incorporates leading edge CMOS technology as well as SIEMENS’
many years’ experience in Telecommunication ICs.
In communication links reflections resulting in an electrical echo are due to hybrid splits
or imperfect terminations in subscriber loops. Acoustical echoes may occur due to poor
isolation of microphone and speaker of some telephone system. These electrical and
acoustical echoes disturb the quality of the transmission. To ensure high quality, pure
data
transmission
the
ITU-T
(International
Telecommunications
Union,
Telecommunication Standardization Sector) suggests in the recommendation G.131 the
use of echo cancellers. Echo cancellation is extremely desirable for data links with total
round trip transmission times of more than 50 ms.
Preliminary Product Overview
5
04.99
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