ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8521 is a low skew, 1-to-9 Differential-to-HSTL
Fanout Buffer. The ICS8521 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
F
EATURES
•
9 HSTL outputs
•
Selectable differential CLK, nCLK or LVPECL clock inputs
•
CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, HSTL, SSTL, HCSL
•
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
•
Maximum output frequency: 500MHz
•
Output skew: 50ps (maximum)
•
Part-to-part skew: 250ps (maximum)
•
Propagation delay: 1.8ns (maximum)
•
V
OH
= 1.4V (maximum)
•
3.3V core, 1.8V output operating supply voltages
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
P
IN
A
SSIGNMENT
V
DDO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
32 31 30 29 28 27 26 25
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
DDO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
DDO
ICS8521
9 1 0 1 1 1 2 1 3 1 4 1 5 16
V
DDO
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
DDO
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Y Package
Top View
8521BY
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1
REV. E JULY 25, 2010
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9, 16, 17,
24, 25, 32
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
Name
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
CLK_EN
V
DDO
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3 Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Input
Input
Power
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup
Pulldown
Pullup
Pulldown
Pulldown
Pullup
Type
Description
Core supply pin.
Non-inver ting differential clock input.
Inver ting differential clock input.
Clock select input. When HIGH, selects PCLK, nPCLK inputs.
When LOW, selects CLK, nCLK.
LVTTL / LVCMOS interface levels.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When LOW, Q outputs are forced low, nQ outputs
are forced high. LVCMOS /LVTTL interface levels.
Output supply pins.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
Differential output pair. HSTL interface level.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum Typical
4
51
51
Maximum Units
pF
KΩ
KΩ
8521BY
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2
REV. E JULY 25, 2010
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
CLK_SEL
0
1
0
Selected Sourced
CLK, nCLK
PCLK, nPCLK
CLK, nCLK
Q0:Q8
Disabled; LOW
Disabled; LOW
Enabled
Outputs
nQ0:nQ8
Disabled; HIGH
Disabled; HIGH
Enabled
1
1
PCLK, nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described
in Table 3B.
nCLK, nPCLK
CLK, PCLK
Disabled
Enabled
CLK_EN
nQ0:nQ8
Q0:Q8
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK or PCLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK or nPCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q8
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ8
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
NOTE 1: Please refer to the Application Information "Wiring the Differential Input to Accept Single Ended Levels".
8521BY
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3
REV. E JULY 25, 2010
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
1.6
Typical
3.3
1.8
60
Maximum
3.465
2.0
80
Units
V
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
CLK_EN, CLK_SEL
CLK_EN, CLK_SEL
Input High Current
Input Low Current
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
IN
= V
DD
= 3.465V
V
IN
= V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
V
IN
= 0V, V
DD
= 3.465V
-5
-150
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
V
CMR
0.5
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
8521BY
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4
REV. E JULY 25, 2010
ICS8521
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
1
V
DD
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.3
Common Mode Input Voltage;
V
CMR
1.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
T
ABLE
4E. HSTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
Output High Voltage;
V
OH
NOTE 1
Output Low Voltage;
V
OL
NOTE 1
V
OX
V
SWING
Output Crossover Voltage
Test Conditions
Minimum
1.0
0
40% x (V
OH
- V
OL
) + V
OL
0.6
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.1
Units
V
V
V
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to ground.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= 0°C
TO
70°C
Symbol
f
MAX
t
PD
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
IJ 250MHz
1
Test Conditions
Minimum
Typical
Maximum
500
1.8
50
250
700
700
52
Units
MHz
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
48
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
Measured from V
DD
/2 to the output differential crossing point for single ended input levels.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. E JULY 25, 2010
微控制器 MCU
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