Integrated
Circuit
Systems, Inc.
ICS85357I-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
F
EATURES
•
High speed differential multiplexer. The device can be
configured as either a 4:1 or 2:1 multiplexer
•
1 differential 3.3V LVPECL output
•
4 selectable CLK, nCLK inputs
•
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 750MHz
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKx input
•
Part-to-part skew: 415ps (maximum)
•
Propagation delay: 1.5ns (maximum)
•
LVPECL mode operating voltage supply range:
V
CC
= 3.135V to 3.465V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.135V to -3.465V
•
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS85357I-01 is a 4:1 or 2:1 Differential-to-
3.3V LVPECL / ECL clock multiplexer which can
HiPerClockS™
operate up to 750MHz and is a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS85357I-01 has 4
selectable clock inputs. The CLK, nCLK pair can accept most
standard differential input levels. The device can operate
using a 3.3V LVPECL (V
EE
= 0V, V
CC
= 3.135V to 3.465V) or
3.3V ECL (V
CC
= 0V, V
EE
= -3.135V to -3.465V). The fully dif-
ferential architecture and low propagation delay make it
ideal for use in clock distribution circuits. The select pins have
internal pulldown resistors. Leaving one input unconnected
(pulled to logic low by the internal resistor) will transform
the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins
will select the same numbered data input (i.e., 00
selects CLK0, nCLK0).
ICS
B
LOCK
D
IAGRAM
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
00
P
IN
A
SSIGNMENT
V
CC
CLK0
nCLK0
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
V
EE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
SEL1
SEL0
V
CC
Q0
nQ0
V
CC
nc
nc
V
EE
01
Q0
nQ0
10
11
ICS85357I-01
SEL1 SEL0
20-Lead TSSOP
4.40mm x 6.50mm x 0.90mm body package
G Package
Top View
85357AGI-01
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 11, 2004
Integrated
Circuit
Systems, Inc.
ICS85357I-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
Type
Power
Input
Input
Input
Input
Input
Input
Input
Input
Power
Unused
Output
Input
Input
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
Description
Positive supply pins.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Non-inver ting differential clock input.
Inver ting differential clock input.
Negative supply pins.
No connect.
Differential output pairs. LVPECL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
Clock select input. LVCMOS / LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 14,
17, 20
2
3
4
5
6
7
8
9
10, 11
12, 13
15, 16
18
19
Name
V
CC
CLK0
nCLK0
CLK1
nCLK1
CL K 2
nCLK2
CLK 3
nCLK3
V
EE
nc
nQ0, Q0
S E L0
SEL1
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
T
ABLE
3. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
SEL1
0
0
1
1
SEL0
0
1
0
1
Clock Out
CLK
CLK0, nCLK0
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
85357AGI-01
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 11, 2004
Integrated
Circuit
Systems, Inc.
ICS85357I-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
35
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL0, SEL1
SEL0, SEL1
SEL0, SEL1
SEL0, SEL1
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
Units
V
V
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
Parameter
CLK0, CLK1,
CLK2, CLK3
Test Conditions
V
CC
= V
IN
= 3.465V
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
1.3
V
CC
- 0.85
V
V
nCLK0, nCLK1,
V
CC
= V
IN
= 3.465V
nCLK2, nCLK3
CLK0, CLK1,
-5
V
CC
= 3.465V, V
IN
= 0V
CLK2, CLK3
I
IL
Input Low Current
nCLK0, nCLK1,
V
CC
= 3.465V, V
IN
= 0V
-150
nCLK2, nCLK3
V
PP
Peak-to-Peak Voltage
0.15
Common Mode Input Voltage;
V
CMR
V
EE
+ 0.5
NOTE 1, 2
NOTE 1: Common mode input voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is V
CC
+ 0.3V.
I
IH
Input High Current
85357AGI-01
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 11, 2004
Integrated
Circuit
Systems, Inc.
ICS85357I-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
-1.7
1.0
Units
V
V
V
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
OH
V
OL
V
SWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PD
Parameter
Maximum Output Frequency
Propagation Delay; NOTE 1
Par t-to-Par t Skew; NOTE 2, 3
Output Rise/Fall Time
20% to 80%
200
1
Test Conditions
Minimum
Typical
Maximum
750
1.5
415
700
Units
MHz
ns
ps
ps
%
t
sk(pp)
t
R
/ t
F
odc
Output Duty Cycle
46
54
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
85357AGI-01
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 11, 2004
Integrated
Circuit
Systems, Inc.
ICS85357I-01
4:1
OR
2:1
D
IFFERENTIAL
-
TO
-3.3V LVPECL / ECL C
LOCK
M
ULTIPLEXER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
2V
V
CC
Qx
SCOPE
V
CC
LVPECL
V
EE
nQx
nCLK0:
nCLK3
V
CLK0:
CLK3
V
EE
PP
Cross Points
V
CMR
-1.3V ± -0.165V
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
D
IFFERENTIAL
I
NPUT
L
EVEL
PART 1
nCLK0:
nCLK3
CLK0:
CLK3
nQ0
Q0
Qx
PART 2
Qy
t
sk(o)
t
PD
P
ART
-
TO
-P
ART
S
KEW
P
ROPAGATION
D
ELAY
nQ0
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
Q0
Pulse Width
t
PERIOD
odc =
t
PW
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
85357AGI-01
O
UTPUT
D
UTY
C
YLE
/P
ULSE
W
IDTH
/P
ERIOD
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 11, 2004
嵌入式系统
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