QUAD NON-PROGRAMMABLE
PCM CODEC
FEATURES
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821024
DATASHEET
DESCRIPTION
The IDT821024 is a single-chip, four channel PCM CODEC with on-
chip filters. The device provides analog-to-digital and digital-to-analog
conversions and supports both a-law and
μ−law
companding. The digital
filters in IDT821024 provides the necessary transmit and receive filtering for
voice telephone circuit to interface with time-division multiplexed systems.
All of the digital filters are performed in digital signal processors operating
from an internal clock, which is derived from MCLK. The fixed filters set
the transmit and receive gain and frequency response.
In the IDT821024 the PCM data is transmitted to and received from the
PCM highway in time slots determined by the individual Frame Sync signals
(FSR
n
and FSX
n
, where n = 1-4) at rates from 256 KHz to 8.192 MHz. Both
Long and Short Frame Sync modes are available in the IDT821024.
The IDT821024 can be used in digital telecommunication applications
such as PBX, Central Office Switch, Digital Telephone and Integrated
Voice/Data Access Unit.
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4 channel CODEC with on-chip digital filters
Selectable A-law or
μ-law
companding
Master clock frequency selection: 2.048 MHz, 4.096 MHz or
8.192 MHz
- Internal timing automatically adjusted based on MCLK and frame
sync signal
Separate PCM and master clocks
Single PCM port with up to 8.192 MHz data rate (128 time slots)
Transhybrid balance impedance hardware adjustable via external
components
Transmit gains hardware adjustable via external components
Low power +5.0 V CMOS technology
+5.0 V single power supply
Package available: 32 pin PLCC, 44 pin TQFP
FUNCTIONAL BLOCK DIAGRAM
821024 REVISION A JUNE 25, 2014
1
©2014 Integrated Device Technology, Inc.
821024 DATA SHEET
The IDT821024 contains four channel PCM CODEC with on chip digital
filters. It provides the four-wire solution for the subscriber line circuitry in
digital switches. The device converts analog voice signal to digital PCM
data, and converts digital PCM data back to analog signal. Digital filters
are used to bandlimit the voice signals during the conversion. Either A-law
or
μ-law
is supported by the IDT821024. The law selection is performed
by A/μ pin.
The frequency of the master clock (MCLK) can be 2.048 MHz, 4.096 MHz,
or 8.192 MHz. Internal circuitry determines the master clock frequency
automatically.
The serial PCM data for four channels are time multiplexed via two pins,
DX and DR. The time slots of the four channels are determined by the
individual Frame Sync signals at rates from 256 kHz to 8.192 MHz. For
each channel, the IDT821024 provides a transmit Frame Sync signal and
a receive Frame Sync signal.
Each channel of the IDT821024 can be powered down independently to
save power consumption. The Channel Power Down Pins PDN1-4 configure
channels to be active (power-on) or standby (power-down) separately.
Signal Processing
High performance oversampling Analog-to-Digital Converters (ADC) and
Digital-to-Analog Converters (DAC) are used in the IDT821024 to provide
the required conversion accuracy. The associated decimation and interpo-
lation filtering are realized with both dedicated hardware and Digital Signal
Processor (DSP). The DSP also handles all other necessary functions such
as PCM bandpass filtering and sample rate conversion.
Transmit Signal Processing
In the transmit path, the analog input signal is received by the ADC and
converted into digital data. The digital output of the oversampling ADC is
decimated and sent to the DSP. The transmit filter is implemented in the
DSP as a digital bandpass filter. The filtered signal is further decimated
and compressed to PCM format.
FUNCTIONAL DESCRIPTION
Transmit PCM Interface
The transmit PCM interface clocks out 1 byte (8 bits) PCM data out of
DX pin every 125
μs.
The transmit logic, synchronized by the Transmit
Frame Sync signal (FSXn), controls the data transmission. The FSXn
pulse identifies the transmit time slot of the PCM frame for Channel N.
The PCM Data is transmitted serially on DX pin with the Most Significant
Bit (MSB) first. When the PCM data is being output on DX pin, the
TSC
signal will be pulled low.
Receive Signal Processing
In the receive path, the PCM code is received at the rate of 8,000
samples per second. The PCM code is expanded and sent to the DSP
for interpolation. A receive filter is implemented in the DSP as a digital
lowpass filter. The filtered signal is then sent to an oversampling DAC. The
DAC output is post-filtered and delivered at VOUT pin by an amplifier. The
amplifier can drive resistive load higher than 2 KΩ.
Receive PCM Interface
The receive PCM interface clocks 1 byte (8 bits) PCM data into DR
pin every 125
μs.
The receive logic, synchronized by the Receive Frame
Sync signal (FSRn), controls the data receiving process. The FSRn pulse
identifies the receive time slot of the PCM frame for Channel N. The PCM
Data is received serially on DR pin with the Most Significant Bit (MSB) first.
Hardware Gain Setting In Transmit Path
The transmit gain of the IDT821024 for each channel can be set by 2
resistors, R
REF
and R
TXn
(as shown in Figure 1), according to the following
equation:
The receive gain of IDT821024 is fixed and equal to 1.
Figure 1. IDT821024 Transmit Gain Setting for Channel 1
REVISION A 06/25/14
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QUAD NON-PROGRAMMABLE
PCM CODEC
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