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8203-FREQ1VPCNSGT

产品描述LVCMOS Output Clock Oscillator, 6MHz Min, 80MHz Max, GREEN, SMD, 4 PIN
产品类别无源元件    振荡器   
文件大小160KB,共2页
制造商IDT (Integrated Device Technology)
标准  
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8203-FREQ1VPCNSGT概述

LVCMOS Output Clock Oscillator, 6MHz Min, 80MHz Max, GREEN, SMD, 4 PIN

8203-FREQ1VPCNSGT规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
Reach Compliance Codecompliant
其他特性STANDBY; TAPE AND REEL; SUPPLY VOLTAGE 2.5V AND 1.8V ALSO POSSIBLE
最长下降时间1.9 ns
频率调整-机械NO
频率稳定性2000%
JESD-609代码e3
制造商序列号8203
安装特点SURFACE MOUNT
最大工作频率80 MHz
最小工作频率6 MHz
最高工作温度70 °C
最低工作温度
振荡器类型LVCMOS
输出负载4 pF
物理尺寸5.0mm x 3.2mm x 0.9mm
最长上升时间1.9 ns
最大供电电压3.63 V
最小供电电压2.97 V
标称供电电压3.3 V
表面贴装YES
最大对称度45/55 %
端子面层Matte Tin (Sn)
Base Number Matches1

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CrystalFree™ Oscillator
Ultra Low Power Oscillators
8203
PRELIMINARY DATA SHEET
Features
Frequency Range:
Output Type:
Frequency Tolerance:
Supply Voltage:
Power Consumption:
Standby Current:
Standard Package:
Operating Temperature:
6 to 133MHz
CMOS
± 2000 ppm
1.8v - 3.3v
1.9 mA
(@ 1.8v)
<1 uA
5.0 x 3.2 mm
2.5 x 2.0 mm
0 to 70 °C , -20 to 70 °C
-20 to 85 °C, -40 to 85 °C
Specifications
2.5v
6 to 133 MHz
± 2000ppm
This product is rated “Green”, please contact
factory for environmental compliancy information
Specification
Parameter
Supply Voltage
Output Frequency
Frequency Stability
Supply Current
Quiescent Current
Input LOW level
Input HIGH level
Output LOW level
Output HIGH level
Rise/Fall Time
Symbol
VDD
F
OUT
F
STB
IDD
I
STBY
V
IL
V
IH
V
OL
V
OH
T
R
/T
F
1.8v
3.3v
Conditions
VDD ±10%
See ordering code
Total Frequency Stability over temperature, supply variation, aging (1st year at 25°C)
2.0 mA
2.2 mA
Typical; No load condition; 25°C
1 uA (max)
STBY# = GND
0.3 VDD (max)
At STBY# pin
0.7 VDD (min)
0.1 VDD (max)
I
OL
= - 1mA
0.9 VDD (min)
I
OH
= 1mA
2.75ns
2.3 ns
1.9 ns
20% to 80% x VDD. Output load (CL) = 4pF
45% / 55%
For frequencies < 80MHz;
SYM
Symmetry
40% / 60%
For frequencies > 80MHz;
Start-up time
T
ST
4100 us
Output valid time after VDD meets the specified range & STBY# transition
Period Jitter
PJ
RMS
17 ps
6 ps
5 ps
4pF load; 75MHz
Cycle to Cycle Jitter
CCJ
MAX
120 ps
4pF load; 75MHz
50 ps
40 ps
Note: Above specifications are typical unless otherwise specified.
* Stability over temperature, supply variation, 3x reflow, load variation, aging (10 years)
1.9 mA
Package Outline and Dimensions
3.20 ±0.05
0.90 ±0.05
1.20 ±0.05
Pin #1 ID
Chamfer
0.5 x 45°
0.85 ±0.05
0.0-0.05
Typical PCB Land Pattern
2.2
5.0 x 3.2
(mm)
STBY#
5.0 x 3.2mm
VDD
2.5
4L SMD
5.00 ±0.05
2.54
GND
0.203 Ref.
OUT
1.4
1.6
Top View
2.0 ±0.05
Bottom View
0.65 ±0.05
0.75 ±0.05
Pin #1 ID
Chamfer
0.35 x 45°
Side View
1.5
0.0-0.05
0.55 ±0.05
2.5 x 2.0
(mm)
STBY#
1.8
VDD
OUT
0.8
2.5 x 2.0mm
4L SMD
2.5 ±0.05
1.225 Bsc
0.152 Ref.
GND
0.9
0.9
Top View
Bottom View
Side View
June 1, 2011
www.IDT.com
©2011 Integrated Device Technology, Inc

 
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