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Datasheet> 器件分类 > 可编程逻辑器件> 可编程逻辑> EP1810JC68-35

EP1810JC68-35: 产品描述UV PLD, 40ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68; 产品类别可编程逻辑器件可编程逻辑; 文件大小227KB，共8页; 制造商Altera (Intel)

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EP1810JC68-35概述

UV PLD, 40ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68

EP1810JC68-35规格参数

参数名称	属性值
零件包装代码	LCC
包装说明	WQCCJ,
针数	68
Reach Compliance Code	unknown
其他特性	48 MACROCELLS; SHARED INPUT/CLOCK
最大时钟频率	28.6 MHz
JESD-30 代码	S-CQCC-J68
长度	24.13 mm
专用输入次数	12
I/O 线路数量	48
端子数量	68
最高工作温度	70 °C
最低工作温度
组织	12 DEDICATED INPUTS, 48 I/O
输出函数	MACROCELL
封装主体材料	CERAMIC, METAL-SEALED COFIRED
封装代码	WQCCJ
封装形状	SQUARE
封装形式	CHIP CARRIER, WINDOW
可编程逻辑类型	UV PLD
传播延迟	40 ns
认证状态	Not Qualified
座面最大高度	5.08 mm
最大供电电压	5.25 V
最小供电电压	4.75 V
标称供电电压	5 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
宽度	24.13 mm
Base Number Matches	1

EP1810JC68-35相似产品对比

	EP1810JC68-35	EP1810LM68-45	EP1810JC68-20	EP1810JC68-25	EP1810JC68-45	EP1810JI68-25	EP1810JI68-45	EP1810JM68-45	EP1810GM68-45
描述	UV PLD, 40ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	OT PLD, 50ns, CMOS, PQCC68, PLASTIC, LCC-68	UV PLD, 22ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 28ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 50ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 28ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 50ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 50ns, CMOS, CQCC68, WINDOWED, CERAMIC, JLCC-68	UV PLD, 50ns, CMOS, CPGA68, WINDOWED, CERAMIC, PGA-68
零件包装代码	LCC	LCC	LCC	LCC	LCC	LCC	LCC	LCC	PGA
包装说明	WQCCJ,	QCCJ,	WQCCJ,	WQCCJ,	WQCCJ,	WQCCJ,	WQCCJ,	WQCCJ,	WPGA,
针数	68	68	68	68	68	68	68	68	68
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
其他特性	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK	48 MACROCELLS; SHARED INPUT/CLOCK
最大时钟频率	28.6 MHz	22.2 MHz	50 MHz	40 MHz	22.2 MHz	40 MHz	22.2 MHz	22.2 MHz	22.2 MHz
JESD-30 代码	S-CQCC-J68	S-PQCC-J68	S-CQCC-J68	S-CQCC-J68	S-CQCC-J68	S-CQCC-J68	S-CQCC-J68	S-CQCC-J68	S-CPGA-P68
长度	24.13 mm	24.2316 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	27.94 mm
专用输入次数	12	12	12	12	12	12	12	12	12
I/O 线路数量	48	48	48	48	48	48	48	48	48
端子数量	68	68	68	68	68	68	68	68	68
最高工作温度	70 °C	125 °C	70 °C	70 °C	70 °C	85 °C	85 °C	125 °C	125 °C
最低工作温度	-	-55 °C	-	-	-	-40 °C	-40 °C	-55 °C	-55 °C
组织	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O	12 DEDICATED INPUTS, 48 I/O
输出函数	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
封装主体材料	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	WQCCJ	QCCJ	WQCCJ	WQCCJ	WQCCJ	WQCCJ	WQCCJ	WQCCJ	WPGA
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	CHIP CARRIER, WINDOW	CHIP CARRIER	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	CHIP CARRIER, WINDOW	GRID ARRAY, WINDOW
可编程逻辑类型	UV PLD	OT PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD	UV PLD
传播延迟	40 ns	50 ns	22 ns	28 ns	50 ns	28 ns	50 ns	50 ns	50 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	5.08 mm	4.953 mm
最大供电电压	5.25 V	5.5 V	5.25 V	5.25 V	5.25 V	5.5 V	5.5 V	5.5 V	5.5 V
最小供电电压	4.75 V	4.5 V	4.75 V	4.75 V	4.75 V	4.5 V	4.5 V	4.5 V	4.5 V
标称供电电压	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	MILITARY	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	MILITARY	MILITARY
端子形式	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	J BEND	PIN/PEG
端子节距	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	2.54 mm
端子位置	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	QUAD	PERPENDICULAR
宽度	24.13 mm	24.2316 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	24.13 mm	27.94 mm
Base Number Matches	1	1	1	1	1	1	1	1	1

EP1810JC68-35

EP1810JC68-35概述

EP1810JC68-35规格参数

EP1810JC68-35相似产品对比

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