SN74LS259
8-Bit Addressable Latch
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed
for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in eight
addressable latches, and also a 1-of-8 decoder and demultiplexer with
active HIGH outputs. The device also incorporates an active LOW
common Clear for resetting all latches, as well as, an active LOW
Enable.
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•
•
•
•
•
•
Serial-to-Parallel Conversion
Eight Bits of Storage With Output of Each Bit Available
Random (Addressable) Data Entry
Active High Demultiplexing or Decoding Capability
Easily Expandable
Common Clear
LOW
POWER
SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
16
1
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS259N
SN74LS259D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS259/D
SN74LS259
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
C
15
E
14
D
13
Q
7
12
Q
6
11
Q
5
10
Q
4
9
1
A
o
2
A
1
3
A
2
4
Q
0
5
Q
1
6
Q
2
7
Q
3
8
GND
LOADING
(Note a)
PIN NAMES
A
0
, A
1
, A
2
D
E
C
Q
0
– Q
7
Address Inputs
Data Input
Enable (Active LOW) Input
Clear (Active LOW) Input
Parallel Latch Outputs
HIGH
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
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SN74LS259
LOGIC DIAGRAM
E
14
D
13
1
A
0
2
A
1
A
2
3
15
C
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
4
5
6
7
9
10
11
12
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
MODE SELECTION
E
L
H
L
H
C
H
H
L
L
MODE
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
C E D A
0
L
L
L
L
L
•
•
•
•
•
L
H
L
L
L
L
•
•
•
•
•
L
X
L
H
L
H
•
•
•
•
•
H
X
L
L
H
H
A
1
X
L
L
L
L
•
•
•
•
•
H
X
L
L
L
L
•
•
•
•
•
H
H
A
2
X
L
L
L
L
Q
0
L
L
H
L
L
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
Q
1
L
L
L
L
H
Q
2
L
L
L
L
L
Q
3
L
L
L
L
L
•
•
•
•
•
L
Q
4
L
L
L
L
L
Q
5
L
L
L
L
L
Q
6
L
L
L
L
L
Q
7
L
L
L
L
L
MODE
Clear
Demultiplex
H
X
L
L
H
H
H
X
L
L
L
L
L
Q
N–1
L
H
Q
N–1
Q
N–1
L
L
L
L
L
H
Memory
H H X
H
H
H
H
•
•
•
•
•
H
H
I
L
L
L
•
•
•
•
•
L
L
I
H
L
H
•
•
•
•
•
L
H
Q
N–1
Q
N–1
L
H
Q
N–1
Q
N–1
Q
N–1
Q
N–1
Q
N–1
Addressable
Latch
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
Q
N–1
= Previous Output State
•
•
•
•
•
Q
N–1
Q
N–1
L
H
H
H
H
H
Q
N–1
Q
N–1
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SN74LS259
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
–20
– 0.4
– 100
36
0.5
20
V
µA
mA
mA
mA
mA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Parameter
Turn-Off Delay, Enable to Output
Turn-On Delay, Enable to Output
Turn-Off Delay, Data to Output
Turn-On Delay, Data to Output
Turn-Off Delay, Address to Output
Turn-On Delay, Address to Output
Turn-On Delay, Clear to Output
Min
Typ
22
15
20
13
24
18
17
Max
35
24
32
21
38
29
27
Unit
ns
ns
ns
ns
ns
ns
ns
Test Conditions
C
L
= 15 pF
AC SET-UP REQUIREMENTS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
s
t
W
t
h
t
h
Input Setup Time
Pulse Width, Clear or Enable
Hold Time, Data
Hold Time, Address
Parameter
Min
20
15
5.0
20
Typ
Max
Unit
ns
ns
ns
ns
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4
SN74LS259
AC WAVEFORMS
D
D
t
w
E
t
PHL
Q
OTHER CONDITIONS: C = H, A = STABLE
t
PLH
1.3 V
OTHER CONDITIONS: E = L, C = H, A = STABLE
t
w
1.3 V
Q
1.3 V
t
PHL
1.3 V
1.3 V
t
PLH
1.3 V
Figure 2. Turn-on and Turn-off Delays,
Data to Output
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
A
1
1.3 V
1.3 V
D
t
s
(H)
t
h
(H)
t
s
(L)
t
h
(L)
1.3 V
A
1
Q
1
1.3 V
t
PHL
1.3 V
1.3 V
t
PLH
1.3 V
E
Q
Q=D
Q=D
OTHER CONDITIONS: E = L, C = L, D = H
OTHER CONDITIONS: C = H, A = STABLE
Figure 3. Turn-on and Turn-off Delays,
Address to Output
Figure 4. Setup and Hold Time, Data to Enable
C
1.3 V
t
PHL
A
t
s
E
STABLE ADDRESS
Q
OTHER CONDITIONS: E = H
1.3 V
Figure 5. Turn-on Delay, Clear to Output
OTHER CONDITIONS: C = H
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
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