Preliminary Data Sheet
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Features
•
•
JEDEC PC-133 SDRAM DIMM Compatible
CAS 2 150MHz Modules (2:3:2) @ 150 MHz
•
CAS Latency = 2
•
RAS to CAS Delay = 3
•
Precharge Delay = 2
Fast 4.5 ns Clock Access Time
Overclock Existing PC Systems to 150 MHz +
Ideal for Low Cost 150 MHz Bus Speed Systems
Supports CAS Latency = 2, 3
On-board Serial Presence Detect (SPD)
Unbuffered 168-pin DIMM
4K Refresh / 64 ms
Single 3.3V
±
0.3V Power Supply
Available on-line at
http://www.pc133memory.com
or
http://www.mushkin.com
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
Vss
DQ0
DQ1
DQ2
DQ3
Vdd
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vdd
DQ14
DQ15
CB0
CB1
Vss
NC
NC
Vdd
WE#
DQMB0
DQMB1
S0#
DNU
Vss
A0
A2
A4
A6
A8
A10/AP
BA1
Vdd
Vdd
CK0
Pin
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
Vss
DNU
S2#
DQMB2
DQMB3
DNU
Vdd
NC
NC
CB2
CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vdd
DQ20
NC
NC
CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vdd
DQ28
DQ29
DQ30
DQ31
Vss
CK2
NC
WP
SDA
SCL
Vdd
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
Vss
DQ32
DQ33
DQ34
DQ35
Vdd
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vdd
DQ46
DQ47
CB4
CB5
Vss
NC
NC
Vdd
CAS#
DQMB4
DQMB5
S1#
RAS#
Vss
A1
A3
A5
A7
A9
BA0
A11
Vdd
CK1
RFU
Pin
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
Vss
CKE0
S3#
DQMB6
DQMB7
RFU
Vdd
NC
NC
CB6
CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vdd
DQ52
NC
NC
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vdd
DQ60
DQ61
DQ62
DQ63
Vss
CK3
NC
SA0
SA1
SA2
Vdd
•
•
•
•
•
•
•
•
•
Description
The Enhanced Memory Systems 64MB and 128MB CAS 2
150MHz HSDRAM DIMMs are the fastest unbuffered
SDRAM DIMMs available. Low latency (2:3:2) at 150 MHz
improves performance in high-end desktop publishing and
graphics applications, particularly with UMA system
architectures. The fast 4.5 ns clock access time allows
unbuffered DIMM operation at 150 MHz for lower memory
latency, and lower costs than registered DIMMs.
The 64MB module (SM6408DT-6.6) is organized as 8Mx64,
and the 128MB module (SM12808DT-6.6) is organized as
16Mx64. The 128MB ECC module (SM12809DT-6.6) is
organized as 16Mx72. Each module contains a serial
presence EEPROM programmed by Enhanced Memory
Systems, which contains information on the module type,
module organization, component speed, and other attributes
relevant to the system controller.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 1 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
Pin Descriptions
Symbol
CK0,1,2,3
CKE0,1
Preliminary Data Sheet
Type
Input
Input
Function
Clocks: All SDRAM input signals are sampled on the positive edge of CK.
Clock Enables: CKE activate (high) or deactivate (low) the CK signals. Deactivating the clock initiates the
Power-Down and Self-Refresh operations (all banks idle), or Clock Suspend operation. CKE is synchronous until
the device enters Power-Down and Self-Refresh modes where it is asynchronous until the mode is exited.
Chip Select: S# enables (low) or disables (high) the command decoder. When the command decoder is
disabled, new commands are ignored but previous operations continue.
Command Inputs: Sampled on the rising edge of CK, these inputs define the command to be executed.
Bank Addresses: These inputs define to which of the 4 banks a given command is being applied.
Address Inputs: A0-A11 define the row address during the Bank Activate command. A0-A8 define the column
address during Read and Write commands. A10/AP invokes the Auto-precharge operation. During manual
Precharge commands, A10/AP low specifies a single bank precharge while A10/AP high precharges all banks.
The address inputs are also used to program the Mode Register.
Data I/O: Data bus inputs and outputs. For Write cycles, input data is applied to these pins and must be set-up
and held relative to the rising edge of clock. For Read cycles, the device drives output data on these pins after
the CAS latency is satisfied.
Data I/O Mask Inputs: DQMB0-7 inputs mask write data (zero latency) and acts as a synchronous output enable
(2-cycle latency) for read data.
ECC Check Bits
Power Supply: +3.3 V
Ground
Serial Presence-Detect Data: SDA is a bi-directional pin used to transfer addresses and data into
and data out of the presence-detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize the presence detect data transfer to
and from the module
Presence-Detect Address Inputs: These pins are used to configure the presence detect device.
Serial Presence Detect Write Protect: Active high inhibits writes to the SPD EEPROM. WP must be driven low
for normal read/write operations.
Reserved for Future Use: These pins should be left unconnected.
Do not use.
No connect - open pin.
S0,1,2,3#
RAS#, CAS#,
WE#
BA1, BA0
A0-A11
Input
Input
Input
Input
DQ0-DQ63
Input/
Output
Input
Input/
Output
Supply
Supply
Input/
Output
Input
Input
Input
-
-
-
DQMB0-7
CB0-7
V
DD
V
SS
SDA
SCL
SA0-2
WP
RFU
DNU
NC
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 2 of 12
Revision 1.0
Preliminary Data Sheet
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
64MB DIMM Functional Block Diagram – SM6408DT-6.6
S0#
Clock Wiring
DQMB0
U0
DQ(7:0)
DQMB4
U4
DQ(39:32)
CK0
CK1
CK2
CK3
4 SDRAM+3.3 pf
Termination
4 SDRAM+3.3 pf
Termination
10
CK0,2
SDRAMs
DQMB1
U1
DQ(15:8)
DQMB5
U5
DQ(47:40)
CK1,3
10 pf
Clock Termination
10
S2#
DQMB2
U2
DQ(23:16)
DQMB6
U6
DQ(55:48)
SCL
SA0-2
SDA
Serial PD
WP
47K
DQMB3
U3
DQ(31:24)
DQMB7
U7
DQ(63:56)
BA0
BA1
A0-A11
Vdd
Vss
BA0 SDRAM U0-7
BA1 SDRAM U0-7
A0-A11 SDRAM U0-7
Vdd SDRAM U0-7
Vss SDRAM U0-7
RAS#
CAS#
WE#
CKE0
RAS# SDRAM U0-7
CAS# SDRAM U0-7
WE# SDRAM U0-7
CKE0 SDRAM U0-7
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U7 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 3 of 12
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
128MB DIMM Functional Block Diagram – SM12808DT-6.6
Preliminary Data Sheet
S0#
S1#
DQMB0
DQ(7:0)
U0
U8
DQMB4
DQ(39:32)
Clock Wiring
U4
U12
CK0
CK1
CK2
CK3
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
DQMB1
DQ(15:8)
U1
U9
DQMB5
DQ(47:40)
U5
U13
10
CK0-3
S2#
S3#
DQMB2
DQ(23:16)
U2
U10
DQMB6
DQ(55:48)
SDRAMs
U6
U14
SCL
SA0-2
SDA
Serial PD
WP
47K
DQMB3
DQ(31:24)
U3
U11
DQMB7
DQ(63:56)
U7
U15
BA0
BA1
A0-A11
Vdd
Vss
BA0 SDRAM U0-15
BA1 SDRAM U0-15
A0-A11 SDRAM U0-15
Vdd SDRAM U0-15
Vss SDRAM U0-15
RAS#
CAS#
WE#
CKE0
Vdd
10K
CKE1
RAS# SDRAM U0-15
CAS# SDRAM U0-15
WE# SDRAM U0-15
CKE0 SDRAM U0-7
CKE1 SDRAM U8-15
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U15 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Page 4 of 12
Revision 1.0
Preliminary Data Sheet
CAS2/150MHz HSDRAM
64MB, 128MB DIMM
128MB ECC DIMM Functional Block Diagram – SM12809DT-6.6
S0#
S1#
Clock Wiring
DQMB0
DQ(7:0)
U0
U9
DQMB4
DQ(39:32)
U5
U14
CK0
CK1
CK2
CK3
5 SDRAM
5 SDRAM
4 SDRAM+3.3 pf
4 SDRAM+3.3 pf
DQMB1
DQ(15:8)
U1
U10
DQMB5
DQ(47:40)
U6
U15
10
CK0-3
CB(7:0)
U2
U11
SDRAMs
Note: SDRAM U11 DQM input MUST
be wired to DQMB5
S2#
S3#
DQMB2
DQ(23:16)
U3
U12
DQMB6
DQ(55:48)
SCL
SA0-2
SDA
Serial PD
WP
47K
U7
U16
BA0
BA1
BA0 SDRAM U0-17
BA1 SDRAM U0-17
A0-A11 SDRAM U0-17
Vdd SDRAM U0-17
Vss SDRAM U0-17
DQMB3
DQ(31:24)
U4
U13
DQMB7
DQ(63:56)
U8
U17
A0-A11
Vdd
Vss
RAS#
CAS#
WE#
CKE0
Vdd
10K
CKE1
RAS# SDRAM U0-17
CAS# SDRAM U0-17
WE# SDRAM U0-17
CKE0 SDRAM U0-8
CKE1 SDRAM U9-17
Note: All DQ resistor values are 10 ohms
All CK resistor values are 10 ohms
U0-U15 are SM3603T-6.6
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.0
Page 5 of 12
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
