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CY62167ESL-55FNXI

产品描述Standard SRAM, 1MX16, 55ns, CMOS, PBGA60, WLCSP-60
产品类别存储    存储   
文件大小498KB,共17页
制造商Cypress(赛普拉斯)
标准
下载文档 详细参数 全文预览

CY62167ESL-55FNXI概述

Standard SRAM, 1MX16, 55ns, CMOS, PBGA60, WLCSP-60

CY62167ESL-55FNXI规格参数

参数名称属性值
是否Rohs认证符合
包装说明VFBGA,
Reach Compliance Codecompliant
最长访问时间55 ns
其他特性IT ALSO OPERATES AT 3V AND 5V NOMINAL SUPPLY
JESD-30 代码R-PBGA-B60
长度5.814 mm
内存密度16777216 bit
内存集成电路类型STANDARD SRAM
内存宽度16
功能数量1
端子数量60
字数1048576 words
字数代码1000000
工作模式ASYNCHRONOUS
最高工作温度85 °C
最低工作温度-40 °C
组织1MX16
封装主体材料PLASTIC/EPOXY
封装代码VFBGA
封装形状RECTANGULAR
封装形式GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行PARALLEL
座面最大高度0.568 mm
最大供电电压 (Vsup)1.95 V
最小供电电压 (Vsup)1.65 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式BALL
端子节距0.55 mm
端子位置BOTTOM
宽度4.654 mm
Base Number Matches1

文档预览

下载PDF文档
CY62167ESL MoBL
®
16-Mbit (1 M × 16) Static RAM
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
Features
High speed: 45 ns/55 ns
Temperature range:
Industrial: –40 °C to +85 °C
Wide voltage range: 1.65 V to 1.95 V, 2.2 V to 3.6 V and 4.5 V
to 5.5 V
Ultra-low standby power
Typical standby current at 25 °C = 1.5
A
Typical standby current at 40 °C = 2.5
A
Ultra-low active power
Active current: I
CC
= 2.2 mA (typical) at f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE Features
Automatic power-down when deselected
CMOS for optimum speed and power
Pb-free 60-pin WLCSP packages
reduces power consumption by 99% when addresses are not
toggling. Place the device into standby mode when deselected
(CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH).
The input and output pins (I/O
0
through I/O
15
) are placed in a
high impedance state during the following events:
The device is deselected (CE
1
HIGH or CE
2
LOW)
Outputs are disabled (OE HIGH)
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or a write operation is in progress (CE
1
LOW, CE
2
HIGH and WE LOW)
Write to the device by taking Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
19
). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O
8
through I/O
15
) is written into the location specified on
the address pins (A
0
through A
19
).
Read from the device by taking Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See
Truth Table on page 12
for a complete description of read and write modes.
Functional Description
The CY62167ESL is a high-performance CMOS Static RAM
organized as 1M words by 16 bits. This device features an
advanced circuit design that provides an ultra low active current.
Ultra low active current is ideal for providing More Battery Life
(MoBL
®
) in portable applications such as hand-held devices.
The device also has an automatic power-down feature that
Logic Block Diagram
– CY62167ESL
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
DATA IN DRIVERS
1M × 16
RAM ARRAY
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
CE
2
BHE
Power Down
Circuit
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
CE
1
BHE
BLE
WE
OE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document Number: 001-95928 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised July 16, 2015
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