CY8CLED04
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐
Configurable dimmers support up to four
independent LED channels
❐
8- to 32-bits of resolution per channel
❐
Dynamic reconfiguration enables led controller plus other
features: CapSense
®
, Battery Charging, and Motor Control
Visual embedded design
❐
LED-Based drivers
• Binning compensation
• Temperature feedback
• Optical feedback
• DMX512
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PrISM™ modulation technology
❐
Reduces radiated EMI
❐
Reduces low frequency blinking
®
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Advanced peripherals (PSoC blocks)
❐
Four digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and PWMs
• Full-duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPIO pins
❐
Six Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 9-bit DACs
• Programmable gain amplifiers (PGA)
• Programmable filters and comparators
❐
Complex peripherals by combining blocks
❐
Capacitive sensing application capability
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Complete development tools
❐
Free development software
• PSoC Designer™
❐
Full featured, in-circuit emulator (ICE) and programmer
❐
Full speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
Programmable pin configurations
❐
25 mA sink, 10 mA source on all GPIO
❐
Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐
Up to 12 analog inputs on GPIO
❐
Four 30 mA analog outputs on GPIO
❐
Configurable interrupt on all GPIO
Flexible on-chip memory
❐
16K flash program storage 50,000 erase/write cycles
❐
1K SRAM data storage
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In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Full speed USB (12 Mbps)
❐
Four uni-directional endpoints
❐
One bi-directional control endpoint
❐
USB 2.0 compliant
❐
Dedicated 256 byte buffer
❐
No external crystal required
Cypress Semiconductor Corporation
Document Number: 001-13108 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 13, 2011
CY8CLED04
Logic Block Diagram
Port 7
Port 5 Port 4
Port 3
Port 2 Port 1
Port 0 Analog
Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM
1K
Interrupt
Controller
SROM
Flash 16 K
Sleep and
Watchdog
CPU Core (M8C)
Clock Sources
( Includes IMO and ILO)
DIGITAL SYSTEM
Digital
Block
Array
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Digital
2
Decimator
Clocks MACs
Type 2
I C
2
POR and LVD
System Resets
Internal
Voltage
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Document Number: 001-13108 Rev. *F
Page 2 of 49
CY8CLED04
Contents
EZ-Color™ Functional Overview ..................................... 4
Target Applications ...................................................... 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
The Analog Multiplexer System ................................... 6
Additional System Resources ..................................... 6
EZ-Color Device Characteristics ................................. 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 9
Select User Modules ................................................... 9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pin Information ............................................................... 10
68-Pin Part Pinout ..................................................... 10
Register Conventions .................................................... 11
Abbreviations Used ................................................... 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Operating Temperature ............................................. 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 29
Packaging Information ................................................... 37
Thermal Impedance .................................................. 38
Solder Reflow Peak Temperature ............................. 38
Development Tools ........................................................ 39
Software .................................................................... 39
Evaluation Tools ........................................................ 39
Device Programmers ................................................. 40
Accessories (Emulation and Programming) .............. 40
Third Party Tools ....................................................... 40
Build a PSoC Emulator into Your Board .................... 40
Ordering Information ...................................................... 41
Key Device Features ................................................. 41
Ordering Code Definitions ......................................... 41
Acronyms ........................................................................ 42
Acronyms Used ......................................................... 42
Reference Documents .................................................... 42
Document Conventions ................................................. 43
Units of Measure ....................................................... 43
Numeric Conventions ................................................ 43
Glossary .......................................................................... 43
Document History Page ................................................. 48
Sales, Solutions, and Legal Information ...................... 49
Worldwide Sales and Design Support ....................... 49
Products .................................................................... 49
PSoC® Solutions ...................................................... 49
Document Number: 001-13108 Rev. *F
Page 3 of 49
CY8CLED04
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for high brightness LED applications requiring intelligent
dimming control. EZ-Color devices combine the power and
flexibility of Programmable System-on-Chip (PSoC
®
); with
Cypress's precise illumination signal modulation (PrISM™)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify
implementation of fixed color points through temperature,
optical, and LED binning compensation. EZ-Color's virtually
limitless analog and digital customization enable simple
integration of features in addition to intelligent lighting, such as
CapSense, battery charging, image stabilization, and motor
control during the development process. These features, along
with Cypress's best-in-class quality and design support, make
EZ-Color the ideal choice for intelligent HB LED control
applications.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
The Digital System
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user module references.
Digital peripheral configurations include:
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PrISM (8- to 32-bit)
Full speed USB (12 Mbps)
PWMs (8- to 32-bit)
PWMs with Dead band (8- to 24-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8-bit with selectable parity
SPI master and slave
I
2
C slave and multi-master
Cyclical Redundancy Checker (CRC)/Generator (8- to 32-bit)
IrDA
Generators (8- to 32-bit)
Target Applications
■
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LCD Backlight
Large Signs
General Lighting
Architectural Lighting
Camera/Cell Phone Flash
Flashlights
The PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
General Purpose I/O (GPIO).
The M8C CPU core is a powerful processor with speeds up to
68 MHz, providing a four MIPS 8-bit Harvard-architecture
microprocessor. The CPU uses an interrupt controller with up to
20 vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included Sleep and watchdog timers (WDT).
Memory encompasses 16K of flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The EZ-Color family incorporates flexible internal clock
generators, including a 24 MHz internal main oscillator (IMO)
accurate to 8 percent over temperature and voltage. The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz internal low speed oscillator (ILO) is
provided for the sleep timer and WDT. The clocks, together with
programmable clock dividers (as a system resource), provide the
flexibility to integrate almost any timing requirement into the
EZ-Color device. In USB systems, the IMO self-tunes to ± 0.25%
accuracy for USB communication.
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device
Characteristics.
Figure 1. Digital System Block Diagram
Port 7
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Digital Clocks
From Core
To System Bus
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Document Number: 001-13108 Rev. *F
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CY8CLED04
The Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
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Figure 2. Analog System Block Diagram
All IO
(Except Port 7)
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
Analog
Mux Bus
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
Filters (2 and 4 pole band-pass, low-pass, and notch)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (up to 2, with 16 selectable thresholds)
DACs (up to 2, with 6- to 9-bit resolution)
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
1.3-V reference (as a system resource)
DTMF Dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
Analog blocks are arranged in a column of three, which includes
one Continuous Time (CT) and two Switched Capacitor (SC)
blocks, as shown in the figure below.
Block
Array
ACB00
ASC10
ASD20
ACB01
ASD11
ASC21
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-13108 Rev. *F
Page 5 of 49
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