A43P26161
Preliminary
Document Title
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
Revision History
Rev. No.
0.0
1.0
1.1
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
History
Initial issue
Modify to 133MHz & 105MHz
Modify all DC specification for new product
Modify t
SS
from 3ns to 2ns
Issue Date
September 13, 2004
June 10, 2005
July 11, 2005
Remark
Preliminary
PRELIMINARY
(July, 2005, Version 1.1)
AMIC Technology, Corp.
A43P26161
Preliminary
Features
Low power supply
- VDD: 2.5V VDDQ : 2.5V
LVCMOS compatible with multiplexed address
Four banks / Pulse
RAS
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Deep Power Down Mode
DQM for masking
Auto & self refresh
Clock Frequency (max) : 105MHz @ CL=3 (-95)
133MHz @ CL=3 (-75)
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM
64ms refresh period (4K cycle)
Self refresh with programmable refresh period through
EMRS cycle
Programmable Power Reduction Feature by partial
array activation during Self-refresh through EMRS
cycle
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages.
Package is available to lead free (-F series)
General Description
The A43P26161 is 67,108,864 bits Low Power
synchronous high data rate Dynamic RAM organized as 4
X 1,048,576 words by 16 bits, fabricated with AMIC’s high
performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock.
I/O transactions are possible on every clock cycle. Range
of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high
bandwidth,
high
performance
memory
system
applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
A
B
C
D
E
F
G
H
J
1
VSS
DQ
14
DQ
12
DQ
10
DQ
8
UDQM
NC
A8
VSS
54 Ball (6X9) CSP
2
3
7
DQ
15
VSSQ
VDDQ
DQ
13
VDDQ
VSSQ
DQ
11
VSSQ
VDDQ
DQ
9
VDDQ
VSSQ
NC
VSS
VDD
CLK
CKE
CAS
A11
A7
A5
A9
A6
A4
BA0
A0
A3
8
DQ
0
DQ
2
DQ
4
DQ
6
LDQM
9
VDD
DQ
1
DQ
3
DQ
5
DQ
7
RAS
BA1
A1
A2
WE
CS
A10
VDD
PRELIMINARY
(July, 2005, Version 1.1)
1
AMIC Technology, Corp.
A43P26161
Pin Configuration (continued)
54 TSOP (II)
VDDQ
VSSQ
DQ
15
DQ
12
DQ
14
DQ
13
DQ
11
DQ
10
UDQM
VDDQ
VSSQ
CKE
VSS
VSS
DQ
8
VSS
VDD
CLK
DQ
9
NC
A11
NC
A9
A8
A7
A6
A5
A2
A4
A3
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
A43P26161V
1
VDD
2
DQ
0
3
VDDQ
4
DQ
1
5
DQ
2
6
VSSQ
7
DQ
3
8
DQ
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
VSSQ
CS
BS0
BS1
A0
WE
A10/AP
CAS
VDD
LDQM
VDDQ
RAS
DQ
5
DQ
6
DQ
7
A1
Block Diagram
LWE
I/O Control
Bank Select
Data Input Register
DQM
Row Buffer
Refresh Counter
Row Decoder
1M X 16
1M X 16
1M X 16
1M X 16
Output Buffer
Sense AMP
Address Register
CLK
DQi
LCBR
LRAS
Column Buffer
ADD
Column Decoder
Latency & Burst Length
LRAS
LCAS
LRAS
LCBR
LWE
LWCBR
Timing Register
Programming Register
DQM
CLK
CKE
CS
RAS
CAS
WE
DQM
PRELIMINARY
(July, 2005, Version 1.1)
2
AMIC Technology, Corp.
A43P26161
Pin Descriptions
Symbol
Name
Description
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A11
Address
Row address : RA0~RA11, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BS0, BS1
Bank Select Address
Selects band for read/write during column address latch time.
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
RAS
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +2.3V ~ 2.7V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CAS
WE
L(U)DQM
DQ
0-15
VDD/VSS
VDDQ/VSSQ
NC/RFU
PRELIMINARY
(July, 2005, Version 1.1)
3
AMIC Technology, Corp.
A43P26161
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +3.0V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to + 3.0V
Storage Temperature (T
STG
) . . . . . . . . . . -55
°
C to +150
°
C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
°
C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
Parameter
Symbol
Condition
Min
Max
Unit
Input Capacitance
CI1
CI2
A0 to A11, BS0, BS1
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
, DQM
DQ0 to DQ15
2.0
2.0
3.5
4.0
4.0
6.0
pF
pF
pF
Data Input/Output Capacitance
CI/O
DC Electrical Characteristics
Recommend operating conditions
(Voltage referenced to VSS=0V, T
A
= 0ºC to +70ºC for commercial or T
A
=-40ºC to +85ºC for extended)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Supply Voltage
DQ Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
VDD
VDDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
2.3
2.3
0.8*VDDQ
-0.3
VDDQ - 0.2
-
-1
-1.5
2.5
2.5
-
-
-
-
-
-
2.7
2.7
VDDQ+0.3
0.3
-
0.2
1
1.5
V
V
V
V
V
V
µ
A
µ
A
Note 1
I
OH
= -0.1mA
I
OL
= 0.1mA
Note 2
Note 3
See Fig. 1 (Page 6)
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
PRELIMINARY
(July, 2005, Version 1.1)
4
AMIC Technology, Corp.
DSP 与 ARM 处理器
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