M-8870 DTMF Receiver
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Low power consumption
Adjustable acquisition and release times
Central office quality and performance
Power-down and inhibit modes (-02 only)
Inexpensive 3.58 MHz time base
Single 5 volt power supply
Dial tone suppression
Applications include: telephone switch equipment, re-
mote data entry, paging systems, personal computers,
credit card systems
The M-8870 is a full DTMF Receiver that integrates both
bandsplit filter and decoder functions into a single 18-pin DIP or
SOIC package. Manufactured using CMOS process technol-
ogy, the M-8870 offers low power consumption (35 mW max)
and precise data handling. Its filter section uses switched ca-
pacitor technology for both the high and low group filters and for
dial tone rejection. Its decoder uses digital counting techniques
to detect and decode all 16 DTMF tone pairs into a 4-bit code.
External component count is minimized by provision of an
on-chip differential input amplifier, clock generator, and latched
tri-state interface bus. Minimal external components required in-
clude a low-cost 3.579545 MHz color burst crystal, a timing re-
sistor, and a timing capacitor.
Figure 1 Pin Connections
The M-8870-02 provides a “power-down” option which, when
enabled, drops consumption to less than 0.5 mW. The
M-8870-02 can also inhibit the decoding of fourth column digits
(see Table 5).
Figure 2 Block Diagram
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
E-mail: info@teltone.com Internet: www.teltone.com
Page 1
M-8870
Functional Description
M-8870 operating functions (see Figure 2) include a bandsplit
filter that separates the high and low tones of the received pair,
and a digital decoder that verifies both the frequency and dura-
tion of the received tones before passing the resulting 4-bit code
to the output bus.
Filter
The low and high group tones are separated by applying the
dual-tone signal to the inputs of two 6th order switched capacitor
bandpass filters with bandwidths that correspond to the bands
enclosing the low and high group tones. The filter also incorpo-
rates notches at 350 and 440 Hz, providing excellent dial tone
rejection. Each filter output is followed by a single-order
switched capacitor section that smooths the signals prior to lim-
iting. Signal limiting is performed by high-gain comparators pro-
vided with hysteresis to prevent detection of unwanted low-level
signals and noise. The comparator outputs provide full-rail logic
swings at the frequencies of the incoming tones.
Decoder
The M-8870 decoder uses a digital counting technique to deter-
mine the frequencies of the limited tones and to verify that they
correspond to standard DTMF frequencies. A complex averag-
ing algorithm is used to protect against tone simulation by extra-
neous signals (such as voice) while tolerating small frequency
variations. The algorithm ensures an optimum combination of
immunity to talkoff and tolerance to interfering signals (third
tones) and noise. When the detector recognizes the simulta-
neous presence of two valid tones (known as “signal condition”),
it raises the Early Steering flag (ESt). Any subsequent loss of
signal condition will cause ESt to fall.
Steering Circuit
Before a decoded tone pair is registered, the receiver checks for
a valid signal duration (referred to as “charac-
ter-recognition-condition”). This check is performed by an exter-
nal RC time constant driven by ESt. A logic high on ESt causes
VC (see Figure 2) to rise as the capacitor discharges. Provided
that signal condition is maintained (ESt remains high) for the val-
idation period (t
GTF
), V
C
reaches the threshold (V
TSt
) of the
steering logic to register the tone pair, thus latching its corre-
sponding 4-bit code (see Table 3) into the output latch. At this
point, the GT output is activated and drives V
C
to V
DD
. GT con-
tinues to drive high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the “delayed steer-
ing” output flag (StD) goes high, signaling that a received tone
pair has been registered. The contents of the output latch are
made available on the 4-bit output bus by raising the three-state
control input (OE) to a logic high. The steering circuit works in re-
verse to validate the interdigit pause between signals. Thus, as
well as rejecting signals too short to be considered valid, the re-
ceiver will tolerate signal interruptions (dropouts) too short to be
considered a valid pause. This capability, together with the abil-
ity to select the steering time constants externally, allows the de-
signer to tailor performance to meet a wide variety of system
requirements.
Figure 4 Single-Ended Input Configuration
Guard Time Adjustment
Where independent selection of signal duration and interdigit
pause are not required, the simple steering circuit of Figure 3 is
applicable. Component values are chosen according to the for-
mula:
t
REC
= t
DP
+ t
GTP
t
GTP
≅
0.67 RC
The value of t
DP
is a parameter of the device and t
REC
is the mini-
mum signal duration to be recognized by the receiver. A value
for C of 0.1
µF
is recommended for most applications, leaving R
to be selected by the designer. For example, a suitable value of
R for a t
REC
of 40 ms would be 300 kΩ. A typical circuit using this
steering configuration is shown in Figure 4. The timing require-
ments for most telecommunication applications are satisfied
with this circuit. Different steering arrangements may be used to
select independently the guard times for tone-present (t
GTP
) and
tone-absent (t
GTA
). This may be necessary to meet system
specifications that place both accept and reject limits on both
tone duration and interdigit pause.
Figure 3 Basic Steering Circuit
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
E-mail: info@teltone.com Internet: www.teltone.com
Page 2
M-8870
Table 1 Pin Functions
Pin
1
2
3
4
5
6
7
8
9
10
11 - 14
Name
IN+
IN-
GS
V
REF
INH*
PD*
OSC1
OSC2
V
SS
OE
Q1, Q2,
Q3, Q4
StD
Description
Non-inverting input
Connections to the front-end differential amplifier.
Inverting input
Gain select. Gives access to output of front-end amplifier for connection of feedback resistor.
Reference voltage output (nominally V
DD
/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones representing keys A, B, C, and D.
Power down. Logic high powers down the device and inhibits the oscillator. Internal pulldown.
Clock input
3.579545 MHz crystal connected between these pins completes the internal oscillator.
Clock output
Negative power supply (normally connected to 0 V).
Tri-statable output enable (input). Logic high enables the outputs Q1 - Q4. Internal pullup.
Tri-statable data outputs. When enabled by OE, provides the code corresponding to the last valid tone pair received (see
Table 5).
15
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output latch is up-
dated. Returns to logic low when the voltage on St/GT falls below V
TSt
.
16
ESt
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone pair (sig-
nal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
17
St/GT Steering input/guard time output (bidirectional). A voltage greater than V
TSt
detected at St causes the device to register
the detected tone pair and update the output latch. A voltage less than V
TSt
frees the device to accept a new tone pair.
The GT output acts to reset the external steering time constant, and its state is a function of ESt and the voltage on St.
(See Figure 7).
18
V
DD
Positive power supply. (Normally connected to +5V.)
* -02 only. Connect to V
SS
for -01 version
Guard time adjustment also allows the designer to tailor system
parameters such as talkoff and noise immunity. Increasing t
REC
improves talkoff performance, since it reduces the probability
that tones simulated by speech will maintain signal condition
long enough to be registered. On the other hand, a relatively
short t
REC
with a long t
DO
would be appropriate for extremely
noisy environments where fast acquisition time and immunity to
dropouts would be required. Design information for guard time
adjustment is shown in Figure 5.
Power-down and Inhibit Mode ( -02 only)
A logic high applied to pin 6 (PD) will place the device into
standby mode to minimize power consumption. It stops the os-
cillator and the functioning of the filters. On the M-8870-01 mod-
els, this pin is tied to ground (logic low).
Inhibit mode is enabled by a logic high input to pin 5 (INH). It in-
hibits the detection of 1633 Hz. The output code will remain the
same as the previous detected code (see Table 1). On the
M-8870-01 models, this pin is tied to ground (logic low).
Input Configuration
The input arrangement of the M-8870 provides a differential in-
put operational amplifier as well as a bias source (V
REF
) to bias
the inputs at mid-rail. Provision is made for connection of a feed-
back resistor to the op-amp output (GS) for gain adjustment.
In a single-ended configuration, the input pins are connected as
shown in Figure 4 with the op-amp connected for unity gain and
V
REF
biasing the input at 1/2V
DD
. Figure 6 shows the differential
configuration, which permits gain adjustment with the feedback
resistor R
5
.
DTMF Clock Circuit
The internal clock circuit is completed with the addition of a stan-
dard 3.579545 MHz television color burst crystal. The crystal
can be connected to a single M-8870 as shown in Figure 4, or to
a series of M-8870s. As illustrated in Figure 7, a single crystal
can be used to connect a series of M-8870s by coupling the os-
cillator output of each M-8870 through a 30 pF capacitor to the
oscillator input of the next M-8870.
Figure 5 Guard Time Adjustment
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
E-mail: info@teltone.com Internet: www.teltone.com
Page 3
M-8870
Table 2 Absolute Maximum Ratings
Parameter
Power supply voltage (V
DD
- V
SS
)
Voltage on any pin
Current on any pin
Operating temperature
Storage temperature
Symbol
V
DD
V
DC
I
DD
T
A
T
S
Value
6.0 V max
V
SS
-0.3, V
DD
+0.3
10 mA max
-40°C to + 85°C
-65°C to
+
150°C
Note:
Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Table 3 DC Characteristics
Parameter
Operating supply voltage
Operating supply current
Standby supply current (see Note 3)
Power consumption
Low level input voltage
High level input voltage
Input leakage current
Pullup (source) current on OE
Input impedance, signal inputs 1, 2
Symbol
V
DD
I
DD
I
DD
Q
P
O
V
IL
V
IH
I
IH
/I
IL
I
SO
R
IN
8
Min
4.75
3.0
15
3.5
0.1
6.5
10
15.0
Typ*
Max
5.25
7.0
100
35
1.5
Units
V
mA
µ
A
mW
V
V
µA
µA
mΩ
V
V
V
mA
mA
V
Test Conditions
PD=V
DD
f = 3.579 MHz, V
DD
= 5.0 V
V
IN
= V
SS
or V
DD
(see Note 2)
OE = 0 V
@ 1 kHz
V
TSt
2.2
2.5
Steering threshold voltage
V
OL
0.03
No load
Low level output voltage
V
OH
4.97
No load
High level output voltage
I
OL
1.0
2.5
V
OUT
= 0.4 V
Output low (sink) current
0.4
0.8
V
OUT
= 4.6 V
I
OH
Output high (source) current
V
REF
2.4
2.7
No load
Output voltage V
REF
R
OR
10
Output resistance V
REF
kΩ
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
1. All voltages referenced to V
SS
unless otherwise noted. For typical values, V
DD
= 5.0V, V
SS
= 0V, TA = 25°C.
2. Input pins defined as IN+, IN-, or OE.
3. -02 only.
Table 4 Operating Characteristics - Gain Setting Amplifier
Parameter
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Tolerable capacitive load (GS)
Tolerable resistive load (GS)
Symbol
I
N
R
IN
V
OS
PSRR
CMRR
A
VOL
f
C
V
O
C
L
R
L
50
55
60
1.2
3.5
4
±
25
Min
Typ*
±
100
Max
Units
nA
MΩ
mV
dB
dB
dB
MHz
V
P-P
100
50
pF
No load
1 KHz
-3.0V < V
IN
< 3.0V
Test Conditions
V
SS
< V
IN
< V
DD
1.5
RL
≥
100 KΩ to V
SS
kΩ
V
CM
2.5
V
P-P
Common mode range
*Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
Note:
1. All voltages referenced to V
SS
unless otherwise noted. For typical values V
DD
= 5.0 V, V
SS
= 0 V, TA = 25°C.
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
E-mail: info@teltone.com Internet: www.teltone.com
Page 4
M-8870
Table 5 Tone Decoding
F
LOW
F
HIGH
Key (ref.)
OE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
Q3
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
Q2
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
Q1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
697
1209
1
697
1336
2
697
1477
3
770
1209
4
770
1336
5
770
1477
6
852
1209
7
852
1336
8
852
1477
9
941
1336
0
941
1209
F
941
1477
#
697
1633
A
770
1633
B
852
1633
C
941
1633
D
ANY
ANY
ANY
L = logic low, H = logic high, Z = high impedance
Figure 7 Common Crystal Connection
Figure 6 Differential Input Configuration
Ordering Information
M-8870-01
18-pin plastic DIP
M-8870-01SM
18-pin plastic SOIC
M-8870-01SMTR
18-pin plastic SOIC, tape and reel
M-8870-02P
18-pin plastic DIP, power-down
option
M-8870-02S
18-pin plastic SOIC, power-down
option
M-8870-02T
18-pin plastic SOIC, power-down
option, tape and reel
Teltone Corporation, 22121-20th Avenue SE, Bothell, WA 98021-4408 U.S.A
40-406-00011, Rev. E
Phone: 800-426-3926 or 425-487-1515 Fax: 425-487-2288
E-mail: info@teltone.com Internet: www.teltone.com
Page 5
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