Rev 1; 11/03
10-Tap Silicon Delay Line
General Description
The DS1110 delay line is an improved replacement for
the DS1010. It has ten equally spaced taps providing
delays from 5ns to 500ns. The devices are offered in a
standard 16-pin SO or 14-pin TSSOP. The DS1110 series
delay lines provide a nominal accuracy of ±5% or ±2ns,
whichever is greater, at 5V and +25°C. The DS1110
reproduces the input logic state at the tap 10 output after
a fixed delay as specified by the dash number extension
of the part number. The DS1110 is designed to produce
both leading- and trailing-edge delays with equal preci-
sion. Each tap is capable of driving up to ten 74LS type
loads. Dallas Semiconductor can customize standard
products to meet special needs.
♦
All-Silicon, 5V, 10-Tap Delay Line
♦
Improved, Drop-In Replacement for the DS1010
♦
10 Taps Equally Spaced
♦
Delays are Stable and Precise
♦
Leading- and Trailing-Edge Accuracy
♦
Delay Tolerance ±5% or ±2ns, whichever is
Greater, at 5V and +25°C
♦
Economical
♦
Auto-Insertable, Low Profile
♦
Low-Power CMOS
♦
TTL/CMOS Compatible
♦
Vapor Phase, IR, and Wave Solderable
♦
Fast-Turn Prototypes
♦
Delays Specified Over Commercial and Industrial
Temperature Ranges
♦
Custom Delays Available
♦
Standard 16-Pin SO or 14-Pin TSSOP
Features
DS1110
Applications
Communications Equipment
Medical Devices
Automated Test Equipment
PC Peripheral Devices
Pin Configurations
PART
DS1110E-XXX
DS1110S-XXX
IN 1
N.C.
TAP2
2
3
14 V
CC
13 TAP1
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TSSOP
16 SO
TOP VIEW
DS1110E
12 TAP3
11 TAP5
10 TAP7
9
8
TAP9
TAP10
TAP4 4
TAP6 5
TAP8 6
GND 7
Selector Guide appears at end of data sheet.
TSSOP
Pin Configurations continued at end of data sheet.
_____________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Tap Silicon Delay Line
DS1110
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +125°C
Soldering Temperature...................See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V ±5%, T
A
= -40°C to +85°C.)
PARAMETER
Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Active Current
High-Level Output Current
Low-Level Output Current
SYMBOL
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
(Note 1)
(Note 1)
(Note 1)
0V
≤
V
I
≤
V
CC
V
CC
= max, period = min (Note 2)
V
CC
= min, V
OH
= 2.3V
V
CC
= min, V
OL
= 0.5V
12
CONDITIONS
MIN
4.75
2.4
-0.3
-1.0
40
TYP
5.0
MAX
5.25
V
CC
+ 0.3
+0.8
+1.0
150
-1.0
UNITS
V
V
V
µA
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V ±5%, T
A
= -40°C to +85°C.)
PARAMETER
Input Pulse Width
Input-to-Tap Delay
(Delays
≤
40ns)
Input-to-Tap Delay
(Delays > 40ns)
Power-Up Time
Input Period
SYMBOL
t
WI
t
PLH
t
PHL
t
PLH
t
PHL
t
PU
Period
(Note 8)
2 (t
WI
) or 20,
whichever
is greater
(Note 6)
+25°C, 5.0V (Notes 3, 5, 6, 7, 9)
0°C to +70°C (Notes 4–7)
-40°C to +85°C (Notes 4–7)
+25°C, 5.0V (Notes 3, 5, 6, 7, 9)
0°C to +70°C (Notes 4–7)
-40°C to +85°C (Notes 4–7)
CONDITIONS
MIN
10% of
tap 10
-2
-3
-4
-5
-8
-13
Table 1
Table 1
Table 1
Table 1
Table 1
Table 1
+2
+3
+4
+5
+8
+13
200
ms
ns
%
ns
TYP
MAX
UNITS
ns
2
______________________________________________________________________
10-Tap Silicon Delay Line
CAPACITANCE
(T
A
= +25°C.)
PARAMETER
Input Capacitance
SYMBOL
C
IN
CONDITIONS
MIN
TYP
5
MAX
10
UNITS
pF
DS1110
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All voltages are referenced to ground.
Measured with outputs open.
Initial tolerances are ± with respect to the nominal value at +25°C and V
CC
= 5.0V for both leading and trailing edges.
Temperature and voltage tolerances are with respect to the actual delay measured over stated temperature range and a 4.75V
to 5.25V range.
Intermediate delay values are available on a custom basis.
See
Test Conditions
section.
All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other
taps also slow down; tap 3 can never be faster than tap 2.
Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.)
For Tap 1 delays greater than 20ns, the tolerance is ±3ns or ±5%, whichever is greater.
Typical Operating Characteristics
(V
CC
= 5.0V, T
A
= +25°C, unless otherwise noted.)
DS1110-500 ACTIVE CURRENT
vs. INPUT FREQUENCY
DS1110 toc01
DS1110-50 ACTIVE CURRENT
vs. INPUT FREQUENCY
180
160
ACTIVE CURRENT (mA)
140
120
100
80
60
40
20
0
10
0.1
1.0
15pF LOAD/TAP
V
CC
= 5.25V
10
100
DS1110 toc02
40
35
ACTIVE CURRENT (mA)
30
25
20
15
10
5
0
0.1
1.0
FREQUENCY (MHz)
15pF LOAD/TAP
V
CC
= 5.25V
200
FREQUENCY (MHz)
DS1110-500 TAP 10 DELAY
vs. TEMPERATURE
DS1110 toc03
DS1110-50 TAP 10 DELAY
vs. TEMPERATURE
53
52
DS1110 toc04
575
550
525
DELAY (ns)
54
DELAY (ns)
500kHz INPUT
51
50
49
48
500
475
450
425
-40
-15
10
35
60
85
TEMPERATURE (°C)
47
46
-40
-15
10
35
60
85
TEMPERATURE (°C)
_____________________________________________________________________
3
10-Tap Silicon Delay Line
DS1110
Typical Operating Characteristics (continued)
(V
CC
= 5.0V, T
A
= +25°C, unless otherwise noted.)
DS1110-500 DELAY vs. TAP
DS1110 toc05
DS1110-50 DELAY vs. TAP
45
40
35
DELAY (ns)
FALLING EDGE
DS1110 toc06
500
450
400
350
DELAY (ns)
300
250
200
150
100
50
0
1
2
3
4
5
TAP
6
7
8
9
500kHz INPUT
RISING EDGE
FALLING EDGE
50
30
25
20
15
10
5
0
RISING EDGE
10
1
2
3
4
5
TAP
6
7
8
9
10
DS1110-500 TAP 10 DELAY
vs. VOLTAGE
DS1110 toc07
DS1110-50 TAP 10 DELAY
vs. VOLTAGE
DS1110 toc08
540
55
53
520
DELAY (ns)
DELAY (ns)
FALLING EDGE
500
51
FALLING EDGE
49
RISING EDGE
47
480
RISING EDGE
500kHz INPUT
460
4.750
4.875
5.000
VOLTAGE (V)
5.125
5.250
45
4.750
4.875
5.000
VOLTAGE (V)
5.125
5.250
Pin Description
PIN
NAME
TSSOP
1
2
7
13, 3, 12, 4, 11,
5, 10, 6, 9, 8
14
SO
1
2, 3, 15
8
14, 4, 13, 5, 12, 6, 11,
7, 10, 9
16
IN
N.C.
GND
Tap 1–Tap 10
V
CC
Input
No Connection
Ground
Tap Output Number
5.0V
FUNCTION
4
______________________________________________________________________
10-Tap Silicon Delay Line
Detailed Description
The DS1110 delay line is an improved replacement for
the DS1010. It has ten equally spaced taps providing
delays from 5ns to 500ns. The devices are offered in a
standard 16-pin SO or 14-pin TSSOP. The DS1110
series delay lines provide a nominal accuracy of ±5%
or ±2ns, whichever is greater, at 5V and +25°C. The
DS1110 reproduces the input logic state at the tap 10
output after a fixed delay as specified by the dash
number extension of the part number. The DS1110 is
designed to produce both leading- and trailing-edge
delays with equal precision. Each tap is capable of dri-
ving up to ten 74LS type loads. Dallas Semiconductor
can customize standard products to meet special
needs. For special requests call 972-371-4348.
DS1110
Table 1. Part Number by Delay (t
PHL
, t
PLH
)
PART
DS1110-50
DS1110-60
DS1110-75
DS1110-80
DS1110-100
DS1110-125
DS1110-150
DS1110-175
DS1110-200
DS1110-250
DS1110-300
DS1110-350
DS1110-400
DS1110-450
DS1110-500
TOTAL DELAY* (ns)
50
60
75
80
100
125
150
175
200
250
300
350
400
450
500
DELAY/TAP (ns)
5
6
7.5
8
10
12.5
15
17.5
20
25
30
35
40
45
50
*Custom
delays are available.
TAP1
TAP2
TAP9
TAP10
IN
10%
10%
10%
10%
Figure 1. Logic Diagram
PERIOD
t
RISE
t
FALL
V
IH
2.2V
1.5V
0.8V
2.2V
1.5V
0.8V
1.5V
IN V
IL
t
WI
t
WI
t
PLH
t
PLH
1.5V
OUT
1.5V
Figure 2. Timing Diagram: Silicon Delay Line
_____________________________________________________________________
5
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