UTC MJE13002 NPN EPITAXIAL SILICON TRANSISTOR
NPN SILICON POWER TRANSISTOR
The UTC MJE13002 designed for use in high–volatge,high
speed,power switching in inductive circuit, It is particularly suited
for 115 and 220V switchmode applications such as switching
regulator’s,inverters,DC-DC converter,Motor control,
Solenoid/Relay drivers and deflection circuits.
FEATURES
*Collector-Emitter Sustaining Voltage:
V
CEO
(sus)=300V.
*Collector-Emitter Saturation Voltage:
V
CE(sat)
=1.0V(Max.) @Ic=1.0A, I
B
=0.25A
*Switch Time- t
f
=0.7μs(Max.) @Ic=1.0A.
1
TO-126
1: BASE
2:COLLECTOR
3: EMITTER
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Collector-Emitter Voltage
Collector-Emitter Voltage
Emitter Base Voltage
Collector Current- Continuous
- Peak (1)
Base Current – Continuous
- Peak (1)
Emitter Current – Continuous
- Peak (1)
Total Power Dissipation @ TA=25℃
Derate above 25℃
Total Power Dissipation @ TC=25℃
Derate above 25℃
Operating and Storage Junction
Temperature Range
SYMBOL
V
CEO
(sus)
V
CEV
V
EBO
Ic
I
CM
I
B
I
BM
I
E
I
EM
P
D
P
D
Tj , Tstg
RATING
300
600
9
1.5
3
0.75
1.5
2.25
4.5
1.4
11.2
40
320
-65 to +150
UNIT
V
V
V
A
A
A
Watts
MW/℃
Watts
MW/℃
℃
THERMAL CHARACTERISTICS
CHARACTERISTIC
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Maximum Load Temperature for Soldering Purposes:
1/8” from Case for 5 Seconds
(1) Pulse Test : Pulse Width=5ms,Duty Cycle≤10%
SYMBOL
RθJC
RθJA
T
L
MAX
3.12
89
275
UNIT
℃/W
℃/W
℃
UTC
UNISONIC TECHNOLOGIES CO. LTD
1
QW-R204-014,B
UTC MJE13002 NPN EPITAXIAL SILICON TRANSISTOR
Designer
's
Data for “Worst Case” Conditions – The Designer
's
Data Sheet permits the design of most circuits
entirely from the information presented. SOA Limit curves – representing boundaries on device characteristics – are
given to facilitate “Worst case” design.
ELECTRICAL CHARACTERISTICS
(Tc=25℃
CHARACTERISTIC
OFF CHARACTERISTICS (1)
Collector-Emitter Sustaining Voltage
(Ic=10 mA , I
B
=0)
Collector Cutoff Current
(V
CEV
=Rated Value, V
BE
(off)=1.5 V)
(V
CEV
=Rated Value, VBE(off)=1.5V,Tc=100℃)
unless otherwise noted)
SYMBOL
V
CEO(SUS)
I
CEV
MIN
300
TYP
MAX
UNIT
V
mA
Emitter Cutoff Current
(V
EB
=9 V, Ic=0)
SECOND BREAKDOWN
Second Breakdown Collector Current with bass forward biased
Clamped Inductive SOA with base reverse biased
ON CHARACTERISTICS (1)
DC Current Gain
(Ic=0.5 A, V
CE
=2 V)
(Ic=1 A, V
CE
=2 V)
Collector-Emitter Saturation Voltage
(Ic=0.5A,I
B
=0.1A)
(Ic=1A,I
B
=0.25A)
(Ic=1.5A,I
B
=0.5A)
(Ic=1A,I
B
=0.25A,Tc=100℃)
Base-Emitter Saturation Voltage
(Ic=0.5A,I
B
=0.1A)
(Ic=1A,I
B
=0.25 A)
(Ic=1A,I
B
=0.25A,Tc=100℃)
DYNAMIC CHARACTERISTICS
Current-Gain-Bandwidth Product
(Ic=100mA,V
CE
=10 V, f=1MHz)
Output Capacitance
(V
CB
=10V,I
E
=0,f=0.1MHz)
SWITCHING CHARACTERISTICS(TABLE 1)
Delay Time
(Vcc=125V,Ic=1A,
Rise Time
IB1=IB2=0.2A,tp=25μs,
Storage Time
Duty Cycle≤1%)
Fall Time
INDUCTIVE LOAD, CLAMPED (TABLE 1,FIGURE 12)
Storage Time
(Ic=1A,Vclamp=300V,
Crossover Time
I
B1
=0.2A,V
BE
(off)=5V,Tc=100℃)
Fall Time
(1) Pulse Test : PW=300
μs,
Duty Cycle≤2%
I
EBO
1
5
1
mA
Is/b
RBSOA
See Figure 10
See Figure 11
h
FE1
h
FE2
V
CE(sat)
8
5
40
25
V
0.5
1
3
1
V
BE(sat)
1
1.2
1.1
f
T
Cob
4
10
21
V
MHz
pF
t
d
t
r
t
s
t
f
t
sv
t
c
t
fi
0.05
0.5
2
0.4
1.7
0.29
0.15
0.1
1
4
0.7
4
0.75
μs
μs
μs
μs
μs
μs
μs
CLASSIFICATION OF HFE1
RANK
RANGE
A
8 ~ 16
B
15 ~ 21
C
20 ~ 26
D
25 ~ 31
E
30 ~ 36
F
35 ~ 40
UTC
UNISONIC TECHNOLOGIES CO. LTD
2
QW-R204-014,B
UTC MJE13002 NPN EPITAXIAL SILICON TRANSISTOR
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 1. DC Current Gain
80
60
hFE,DC CURRENT GAIN
V
CE
,COLLECTOR -EMITTER VOLTAGE (VOLTS)
Figure 2. Collector Saturation Region
2
Tj=150℃
25℃
Tj=25℃
1.6
40
30
20
1.2
Ic=0.1A 0.3A 0.5A
1A
1.5A
-55℃
10
8
6
4
0.8
V
CE
=2V
- - - - - -V
CE
=5V
0.2
0.3
0.5 0.7
1
2
0.4
0
0.02
0.05 0.01
0.02
0.05
0.1
0.2
0.5
1
2
0.02 0.03 0.05 0.07 0.1
I
C
, COLLECTOR CURRENT (AMP)
Figure 3. Base-Emitter Voltage
1.4
0.35
I
B
, BASE CURRENT (AMP)
Figure 4. Collector-Emitter Saturation Region
0.3
V,VOLTAGE (VOLTS)
1.2
V,VOLTAGE (VOLTS)
V
BE
(sat)@I
C
/I
B
=3
- - - - - - V
BE
(on)@V
CE
=2V
0.25
0.2
0.15
0.1
0.05
0
0.02 0.03
I
C
/I
B
=3
Tj=-55℃
25℃
1
Tj=-55℃
25℃
25℃
0.8
0.6
150℃
0.05 0.07 0.1
0.2
0.3
0.5 0.7 1
2
150℃
0.05 0.07 0.1
0.2
0.3
0.5 0.7 1
2
0.4
0.02 0.03
I
C
, COLLECTOR CURRENT (AMP)
Figure 5. Collector Cutoff Region
V
CE
=250V
IC,COLLECTOR CURRENT (米A)
I
C
, COLLECTOR CURRENT (AMP)
Figure 6. Capacitance
500
300
200
V,VOLTAGE (VOLTS)
10
4
10
3
Tj=150℃
125℃
100℃
Cib
10
2
100
70
50
30
20
10
10
1
75℃
50℃
10
0
25℃
Cob
10
-1
REVERSE
-0.2
0
FORWARD
+0.2
+0.4
+0.
6
-0.4
7
5
0.1 0.2
0.5 1
2
5
10
20
50
100 200 500
1000
VBE,BASE-EMITTER VOLTAGE (VOLTS)
V
R
,REVERSE VOLTAGE (VOLTS)
UTC
UNISONIC TECHNOLOGIES CO. LTD
3
QW-R204-014,B
UTC MJE13002 NPN EPITAXIAL SILICON TRANSISTOR
TABLE 1.TEST CONDITIONS FOR DYNAMIC PERFORMANCE
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
RESISTIVE
SWITHCING
+5V
1N4933
33
MJE210
Vcc
L
TEST CIRCUITS
0.001μF
pw 5V
DUTY CYCLE≦10%
tr,tf≦10ns
1k
68
33
1N4933
RB
IB
1k
2N2905
47
1/2W 100
MJE200
Ic
MR826*
Vclamp
R
B
+125V
Rc
TUT
SCOPE
2N2222
1k
+5V
5.1k
T.U.T.
51
*SELECTED FOR≧1kV
VCE
D1
-4.0V
1N4933
0.02μF
NOTE
PW and Vcc Adjusted for Desired Ic
RB Adjusted for Desired IB1
270
-VBE(off)
Coil Data :
FERROXCUBE core #6656
Full Bobbin (-200 Turns) #20
GAP for 30 mH/2 A
Lcoil=50mH
Vcc=20V
Vclamp=300V
Vcc=125V
Rc=125Ω
D1=1N5820 or
Equiv.
RB=47Ω
CIRCUIT
VALUES
OUTPUT WAVEFORMS
TEST WAVEFORMS
Ic
tf CLAMPED
Ic(pk)
t
t1
tf
t1=
VCE or
Vclamp
TIME
t2
t
t1 Adjusted to
Obtain Ic
Lcoil(Ic
pk
)
Vcc
Lcoil(Ic
pk
)
Vclamp
Test Equipment
Scope-Tektronics
475 or Equivalent
+10.3V
25μS
0
-8.5V
t
r
,t
f
<10ns
Duty Cycly=1.0%
R
B
and Rc adjusted
for desired I
B
and Ic
V
CE
t2=
TABLE 2.TYPICAL INDUCTIVE SWITCHING PERFORMANCE
Ic
AMP
0.5
Tc
℃
Tsv
Trv
Tfi
Tti
Tc
μ
s
μ
s
μ
s
0.30
0.30
0.14
0.26
0.10
0.22
μ
s
0.35
0.40
0.05
0.06
0.05
0.08
μ
s
0.30
0.36
0.16
0.29
0.16
0.28
25
1.3
0.23
100
1.6
0.26
1
25
1.5
0.10
100
1.7
0.13
1.5
25
1.8
0.07
100
3
0.08
Note: All Data Recorded in the inductive Switching Circuit Table 1
UTC
UNISONIC TECHNOLOGIES CO. LTD
4
QW-R204-014,B
UTC MJE13002 NPN EPITAXIAL SILICON TRANSISTOR
SWITCHING TIMES NOTE
In resistive switching circuits, rise, fall, and storage times have been defined and apply to both current and voltage
waveforms since they are in phase, However, for inductive loads which are common to SWITCHMODE power
supplies and hammer drivers, current and voltage waveforms are not in phase. Therefore, separate measurements
must be made on each wave form to determine the total switching time, For this reason, the following new terms
have been defined.
tsv=Voltage Storage Time, 90% I
B1
to 10% Vclamp
trv=Voltage Rise Time, 10-90% Vclamp
tfi=Current Fall Time, 90-10% Ic
tti=Current Tail, 10-2% Ic
tc=Crossover Time, 10% Vclamp to 10% IC
An enlarged portion of the inductive switching waveforms is shown in Figure 7 to aid in the visual identity of these
terms.
For the designer, there is minimal switching loss during storage time and the predominant switching power losses
occur during the crossover interval and can be obtained using the standard equation from AN-222:
PSWT=1/2 VccIc (tc)f
In general, trv + tfi≒tc. However, at lower test currents this relationship may not be valid.
As is common with most switching transistor, resistive switching is specified at 25℃ and has become a benchmark
for designers. However, for designers of high frequency converter circuits, the user oriented specifications which
make this a “SWITCHMODE” transistor are the inductive switching speeds (tc and tsv) which are guaranteed at 100
℃
SAFE OPERATING AREA INFORMATION
FORWARD BIAS
There are two limitations on the power handling ability of a transistor: average junction temperature and second
break-down. Safe operating area curves indicate Ic – V
CE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 10 is based on Tc=25℃; T
J
(pk) is variable depending on power level. Second breakdown
pulse limits are valid for duty cycles to 10% but must be derated when Tc≧25℃. Second breakdown limitations do
not derate the same as thermal limitations. Allowable current at the voltages shown on Figure 10 may be found at
any case tem-perature by using the appropriate curve on Figure 12.
T
J
(pk) may be calculated from the data in Figure 10. At high case temperatures, thermal limitations will reduce
the power that can be handled to values less than the limitations imposed by second breakdown.
REVERSE BIAS
For inductive loads, high voltage and high current must be sustained simultaneously during turn–off, in most
cases, with the base to emitter junction reverse biased. Under these conditions the collector voltage must be held to
a safe level at or below a specific value of collector current. This can be accomplished by several means such as
active clamping, RC snubbing, load line shaping, etc. The safe level for these devices is specified as Reverse Bias
Safe Operating Area and represents the voltage–current conditions during re-verse biased turn–off. This rating is
verified under clamped conditions so that the device is never subjected to an ava-lanche mode. Figure 11 gives
RBSOA characteristics.
UTC
UNISONIC TECHNOLOGIES CO. LTD
5
QW-R204-014,B
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