Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Military
[5]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
–55
°
C to +125
°
C
V
CC
5V ± 10%
5V ± 10%
5V ± 10%
Electrical Characteristics
Over the Operating Range
[6]
7C131-15
[3]
7C141-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Leakage
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
–5
–5
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
I
OL
= 4.0 mA
I
OL
= 16.0 mA
[7]
2.2
0.8
+5
+5
–350
Com’l
Mil
Com’l
Mil
135
115
75
65
190
–5
–5
Min.
2.4
0.4
0.5
2.2
0.8
+5
+5
–350
170
–5
–5
Max.
7C130-30
[3]
7C131-25,30
7C140-30
7C141-25,30
Min.
2.4
0.4
0.5
2.2
0.8
+5
+5
–350
120
170
45
65
90
115
15
15
15
15
–5
–5
Max.
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
Min.
2.4
0.4
0.5
2.2
0.8
+5
+5
Max.
7C130-55
7C131-55
7C140-55
7C141-55
Min.
2.4
0.4
0.5
V
V
µA
µA
Max. Unit
V
V
Output Short
V
CC
= Max.,
Circuit Current
[8, 9]
V
OUT
= GND
V
CC
Operating
Supply Current
Standby Current
Both Ports,
TTL Inputs
Standby Current
One Port,
TTL Inputs
Standby Current
Both Ports,
CMOS Inputs
CE = V
IL
,
Outputs Open,
f = f
MAX[10]
CE
L
and CE
R
>
V
IH
, f = f
MAX[10]
–350 mA
110
120
35
45
75
90
15
15
mA
mA
mA
mA
I
SB1
I
SB2
CE
L
or CE
R
> V
IH
, Com’l
Active Port Outputs
Mil
Open,
f = f
MAX[10]
Both Ports CE
L
and Com’l
CE
R
>
Mil
V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V, f = 0
I
SB3
Shaded areas contain preliminary information.
Note:
4. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. T
A
is the “instant on” case temperature
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. This parameter is guaranteed but not tested.
10. At f = f
MAX
, address and data inputs are cycling at the maximum frequency of read cycle of 1/t
RC
and using AC Test Waveforms input levels of GND to 3V.
Document #: 38-06002 Rev. *D
Page 3 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Electrical Characteristics
Over the Operating Range
[6]
(continued)
7C131-15
[3]
7C141-15
Parameter
I
SB4
Description
Standby Current
One Port,
CMOS Inputs
Test Conditions
One Port CE
L
or
Com’l
CE
R
> V
CC
– 0.2V,
Mil
V
IN
> V
CC
– 0.2V
or V
IN
< 0.2V,
Active Port Outputs
Open,
f = f
MAX[10]
Min.
Max.
125
7C130-30
[3]
7C131-25,30
7C140-30
7C141-25,30
Min.
Max.
105
7C130-35,45
7C131-35,45
7C140-35,45
7C141-35,45
Min.
Max.
85
105
7C130-55
7C131-55
7C140-55
7C141-55
Min.
Max. Unit
70
85
mA
Capacitance
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
15
10
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIGAND
SCOPE
Equivalent to:
OUTPUT
R2
347Ω
(a)
THÉVENIN EQUIVALENT
250Ω
1.40V
R1 893Ω
5V
OUTPUT
5 pF
INCLUDING
JIGAND
SCOPE
R2
347Ω
(b)
3.0V
GND
10%
ALL INPUT PULSES
90%
90%
10%
≤5ns
BUSY
OR
INT
R1 893Ω
5V
281Ω
30
pF
BUSY Output Load
(CY7C130/CY7C131 ONLY)
≤
5 ns
Document #: 38-06002 Rev. *D
Page 4 of 19
CY7C130/CY7C131
CY7C140/CY7C141
Switching Characteristics
Over the Operating Range
[6, 11]
7C131-15
[3]
7C141-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
[12]
Data Hold from Address Change
CE LOW to Data Valid
[12]
OE LOW to Data
Valid
[12]
3
10
3
10
0
15
15
12
12
2
0
12
10
0
10
0
0
25
20
20
2
0
15
15
0
15
0
0
25
30
25
25
2
0
25
15
0
15
5
15
0
25
OE LOW to Low Z
[9, 13, 14]
OE HIGH to High Z
[9, 13, 14]
CE LOW to Low Z
[9, 13, 14]
CE HIGH to High Z
[9, 13, 14]
CE LOW to Power-Up
[9]
CE HIGH to Power-Down
[9]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
Data Set-Up to Write End
Data Hold from Write End
R/W LOW to High Z
[14]
R/W HIGH to Low Z
[14]
0
15
10
3
15
5
15
15
15
0
25
15
3
15
25
25
0
30
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C130-25
[3]
7C131-25
7C140-25
7C141-25
Min.
Max.
7C130-30
7C131-30
7C140-30
7C141-30
Min.
Max.
Unit
WRITE CYCLE
[15]
Shaded areas contain preliminary information.
Note:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30-pF load capacitance.
12. AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
13. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
14. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
15. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
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