MN102H51K
Type
ROM (×16-bit)
×
RAM (× 16-bit)
×
Package
(Old Package)
Minimum Instruction
Execution Time
Interrupts
MN102H51K
256 K
8K
SDIP064-P-0750C
*Pb free
(SDIP064-P-0750)
83 ns (at 3.6 V to 3.0 V, 12 MHz)
External (6 lines)
Internal (30 lines) : Timer
×
11, A/D
×
1, Undefined command
×
1, RESET
×
1, OSD
×
2, Serial
×
4,
I
2
C
×
1, Caption
×
4, Remote control
×
1, Address coincidence
×
4
Caption
• Built-in sync separator
×
2
50
• Common use
8-bit
×
12-ch. (with S/H)
8-bit
×
7-ch.
I/O Pins
I/O
A/D Inputs
D/A Inputs
PWM
4-bit
×
4-ch. (analog R, G, B, YM output)
Special Ports
CRTC
Notes
Remote control reception
3-layer display (graphics, characters, splits)
Remote control input discriminant circuit built-in
Electrical Characteristics
D/A characteristics
Parameter
Symbol
IFS
VO
ea
se
ht v
tp is
:// it
pa fo
na llo
so win
ni g
c. U
co R
.jp L a
/s bo
em u
ic t la
on te
/e st
-in in
de for
x. ma
ht t
m ion
l
.
Limit
typ
5.0
Condition
min
4.5
RL = 200
Ω,
VREF = 1.2 V, RIREF = 1.2 kΩ
RL = 200
Ω,
VREF = 1.2 V, RIREF = 1.2 kΩ
0.9
RL = 200
Ω,
VREF = 1.2 V, RIREF = 1.2 kΩ
RL = 200
Ω,
VREF = 1.2 V, RIREF = 1.2 kΩ
VREF = 1.2 V, RIREF = 1.2 kΩ, Error from 4-channel average IFS
M
Di ain
sc te
on na
tin nc
ue e/
d
Timer Counter
8-bit timer
×
4
16-bit timer
×
2
Watchdog timer: 17-bit
×
1
Serial Interface
I
2
C
×
1: for multimaster mode, bus line (output) has 2 systems
Sync serial / I
2
C (master) / UART
×
2
Unit
max
5.5
1.1
±
0.5
±
0.5
±
5
mA
V
LSB
LSB
%
D/A full-scale output current
D/A output voltage setting range
D/A non-linear error
NLE
D/A differential non-linear error
D/A channel interval error
Pl
DNLE
IFS
(Ta = 25°C , VDD = AVDD = 3.3 V , VSS = 0 V , fosc = 4 MHz)
160
MAE00014AEM
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semiconductors described in this book
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–
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