Standard Products
MIP 7965
64-Bit Superscaler Microprocessor
October 01, 2010
www.aeroflex.com/Avionics
FEATURES
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Upscreened PMC-Sierra RM7965
Military and Industrial Grades Available
CPU core with MIPS64™ compatible Instruction Set Architecture that features:
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668 & 750 MHz
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Dual-issue superscalar 7-stage pipeline
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16-KB, 4-way set associative L1 Instruction cache
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16-KB, 4-way set associative L1 Data cache
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256-KB, 4-way set associative L2 cache with industry best 5-cycle access latency
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Error Checking and Correcting (ECC) on L2 cache
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Fast Packet Cache™ to assist processing of packet data
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8K-entry branch prediction table
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Fully associative 64-entry TLB with dual pages
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High performance Floating Point unit (IEEE 754)
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Fixed-point DSP instructions such as Multiply/Add, Multiply/Subtract and 3 Operand Multiply
High-performance system interface:
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Multiple outstanding reads with out of order return
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1600 MB/s peak throughput
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Multiplexed address/data bus (SysAD) supports 3.3V I/logic
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Processor clock multipliers 2, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 8.5, 9, 10, 11, 12, 13, 14, 15, 16, 17
Integrated on-chip EJTAG controller
64-entry dynamic Trace Buffer for use in real-time trace and debug
Two 32-bit virtually addressed Watch registers
Integrated performance counters:
– Contains 2 independent 32-bit counters
– Counts over 30 processor events including mispredicted branches
– Enables full characterization and analysis of application software
MIP7965 is available in a 256-TBGA package (27x27 mm):
– MIP7965 (256-TBGA) is pin compatible with RM7065C and RM7065A TBGA products.
– MIP7965 (208-lead CQFP, cavity-up package (F17)) is pin compatible with the ACT7000ASC
– MIP7965 (208-lead CQFP, inverted footprint (F24)), is pin compatible and with the same pin rotation
as the commercial PMC-Sierra RM5261A
NOTE: *MIPS64 and Fast Packet Cache are Trademarks of PMC-Sierra
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SCD7965 Rev H
BLOCK DIAGRAM
SCD7965 Rev H 10/01/10
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INTRODUCTION
The MIP7965 comprise a new family of high-performance 64-bit microprocessors. This product is optimized for performance with
features including a seven-stage dual-issue pipeline, tightly coupled L1 and L2 caches, and sophisticated branch prediction for
maintaining pipeline efficiency.
A 200 MHz 64-bit multiplexed system address and data bus (SysAD) enables a high-bandwidth I/O interface to a variety of system
controllers providing connectivity to a wide range of networking peripherals. All products also contain vectored and prioritized
interrupt controllers for versatile interrupt configurations.
On-chip EJTAG debug modules ensure smooth and easy debugging for both hardware and software by allowing single-step and state
examination. The inclusion of a pipeline-rate branch instruction trace buffer facilitates debugging under operating conditions.
The MIP7965 is available in a 256-TBGA and 208-lead CQFP package. The 256-TBGA package is pin compatible with previous
RM7065x devices. The RM7965 products offer a cost advantage by eliminating the L3 cache controller functionality available with the
RM7900.
For additional Detail Information regarding the operation of the PMC-Sierra see the latest PMC-Sierra datasheet for the RM79xx
Family Microprocessors Data Sheet (doc. # PMC-2030581), Issue No. 11: September, 2006
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PIN DESCRIPTIONS
The following is a list of control, data, clock, interrupt, and miscellaneous pins of MIP7965.
System Interface
PIN NAME
ExtRqst*
Release*
RdRdy*
WrRdy*
ValidIn*
TYPE
Input
Output
Input
Input
Input
DESCRIPTION
External request
Signals that the external agent is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write request.
Valid Input
Signals that an external agent is now driving a valid address or data on the bus and a valid
command or data identifier on the SysCmd bus.
Valid output
Signals that the processor is now driving a valid address or data on the SysAD bus and a valid
command or data identifier on the SysCmd bus.
Processor Request
When asserted this signal requests that control of the system interface be returned to the
processor.
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the processor that it has been
granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor when it is about to return a
memory reference out of order; i.e., of two outstanding memory references, the data for the
second reference is being returned ahead of the data for the first reference. In order that the
processor will have time to switch the address to the tertiary cache, this signal must be asserted
a minimum of two cycles prior to the data itself being presented. Note that this signal works as
a toggle; i.e., for each cycle that it is held asserted the order of return is reversed. By default,
anytime the processor issues a second read it is assumed that the reads will be returned in
order; i.e., no action is required if the reads are indeed returned in order.
Read Type
During the address cycle of a read request, RdType indicates whether the read request is an
instruction read or a data read.
System address/data bus
A 64-bit address and data bus for communication between the processor and an external agent.
System address/data check bus
An 8-bit bus containing parity check bits for the SysAD bus during data cycles.
System command/data identifier bus
A 9-bit bus for command and data identifier transmission between the processor and an
external agent.
System Command/Data Identifier Bus Parity
For the RM79xx, unused on input and zero on output.
ValidOut*
Output
PRqst*
Output
PAck*
Input
RspSwap*
Input
RdType
Output
SysAD[63:0]
SysADC[7:0]
SysCmd[8:0]
Input/Output
Input/Output
Input/Output
SysCmdP
Input/Output
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Clock/Control Interface
PIN NAME
SysClock
TYPE
Input
DESCRIPTION
System clock
Master clock input used as the system interface reference clock. All output timings are relative
to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the
factor selected during boot initialization.
Power Supply
PIN NAME
VccInt
VccIO
VccP
TYPE
Input
Input
Input
DESCRIPTION
Power supply for core.
Power supply for I/O.
Vcc for PLL
Quiet VccInt for the internal phase locked loop. Must be connected to VccInt through a filter
circuit. Note: Not applicable for the F17, F24 QFPs which incorporates the filter components
except for the 10µF capacitor. See "PLL Analog Power Filtering" section herein.
Power supply used for JTAG.
Ground Return.
Vss for PLL
Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
Note: Not applicable for the F17, F24 QFPs which incorporates the filter components except
for the 10µF capacitor. See "PLL Analog Power Filtering" section herein.
VccJ
Vss
VssP
Input
Input
Input
Interrupt Interface
PIN NAME
INT[9:0]*
NMI*
TYPE
Input
Input
DESCRIPTION
Interrupt
Ten general processor interrupts, bit-wise ORed with bits 9:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 15 of the interrupt register..
JTAG Interface
PIN NAME
JTDI/DBDI
JTCK/DBCK
JTDO/DBDO
JTMS/DBMS
JTRST*/DBRST*
JTAGSEL
TYPE
Input
Input
Output
Input
Input
Input
DESCRIPTION
JTAG/EJTAG data in
JTAG/EJTAG serial data in.
JTAG/EJTAG clock input
JTAG/EJTAG serial clock input.
JTAG/EJTAG data out
JTAG/EJTAG serial data out.
JTAG/EJTAG command
JTAG/EJTAG command signal, signals that the incoming serial data is command data.
JTAG/EJTAG reset.
JTAG/EJTAG select Selects
JTAG when JTAGSEL=1; selects EJTAG when JTAGSEL=0
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