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CY14B256K
256 Kbit (32K x 8) nvSRAM with Real Time Clock
Features
■
■
■
■
25 ns, 35 ns, and 45 ns Access Times
Pin Compatible with STK17T88
Data Integrity of Cypress nvSRAM combined with full featured
Real Time Clock
❐
Low power, 350 nA RTC current
❐
Capacitor or battery backup for RTC
Watchdog Timer
Clock Alarm with Programmable Interrupts
Hands Off Automatic
STORE
on Power Down with only a small
Capacitor
STORE
to QuantumTrap initiated by Software, Device Pin, or
on Power Down
RECALL
to SRAM initiated by Software or on Power Up
Infinite
READ, WRITE,
and
RECALL
Cycles
■
■
■
High Reliability
❐
Endurance to 200K cycles
❐
Data retention: 20 years at 55°C
Single 3V Operation with tolerance of +20%, -10%
Commercial and Industrial Temperature
48-Pin SSOP (ROHS compliant)
■
■
■
■
■
■
Logic Block Diagram
en
de
d
fo
The real time clock function provides an accurate clock with leap
year tracking and a programmable high accuracy oscillator. The
alarm function is programmable for one time alarms or periodic
seconds, minutes, hours, or days. There is also a programmable
watchdog timer for process control.
rN
QuantumTrap
512 X 512
STORE
ew
V
CC
The Cypress CY14B256K combines a 256 Kbit nonvolatile static
RAM with a full-featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
QuantumTrap technology producing the world’s most reliable
nonvolatile memory. The SRAM is read and written an infinite
number of times, while independent, nonvolatile data resides in
the nonvolatile elements.
D
V
CAP
RTC
MUX
ROW DECODER
om
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
m
A
5
POWER
CONTROL
STORE/
RECALL
CONTROL
STATIC RAM
ARRAY
512 X 512
RECALL
ec
es
i
V
RTCbat
V
RTCcap
SOFTWARE
DETECT
gn
HSB
Functional Description
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
R
COLUMN IO
COLUMN DEC
INPUT BUFFERS
ot
N
DQ
5
DQ
6
A
0
A
1
A
2
A
3
A
4
A
10
DQ
7
Cypress Semiconductor Corporation
Document Number: 001-06431 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 25, 2009
[+] Feedback
s
A
13
-
A
0
x
1
x
2
INT
A
14
-
A
0
OE
CE
WE
CY14B256K
Contents
Features ............................................................................... 1
Functional Description ........................................................ 1
Logic Block Diagram ........................................................... 1
Contents ............................................................................... 2
Pin Configurations .............................................................. 3
Pin Definitions ..................................................................... 3
Device Operation ................................................................. 4
SRAM READ .................................................................. 4
SRAM WRITE ................................................................ 4
AutoStore Operation ...................................................... 4
Hardware STORE (HSB) Operation............................... 4
Hardware RECALL (Power Up)...................................... 5
Software STORE............................................................ 5
Software RECALL .......................................................... 5
Data Protection .............................................................. 5
Noise Considerations ..................................................... 5
Low Average Active Power ............................................ 6
Best Practices ................................................................ 6
Real Time Clock Operation ................................................. 8
nvTIME Operation .......................................................... 8
Clock Operations............................................................ 8
Reading the Clock .......................................................... 8
Setting the Clock ............................................................ 8
Backup Power ................................................................ 8
Stopping and Starting the Oscillator............................... 8
Calibrating the Clock ...................................................... 9
Alarm .............................................................................. 9
Watchdog Timer ............................................................. 9
Power Monitor ............................................................... 10
Interrupts ...................................................................... 10
Interrupt Register ......................................................... 10
Flags Register .............................................................. 10
Maximum Ratings .............................................................. 16
Operating Range ............................................................... 16
DC Electrical Characteristics ........................................... 16
Data Retention and Endurance ........................................ 17
Capacitance ....................................................................... 17
Thermal Resistance .......................................................... 17
AC Test Conditions ........................................................... 17
AC Switching Characteristics .......................................... 18
AC Switching Characteristics (continued) ...................... 19
AutoStore or Power Up RECALL ..................................... 20
Software Controlled STORE/
RECALL Cycles ................................................................. 21
Hardware STORE Cycle .................................................... 22
Soft Sequence Commands ............................................... 22
RTC Characteristics .......................................................... 23
Truth Table For SRAM Operations .................................. 23
Part Numbering Nomenclature ........................................ 24
Ordering Information ........................................................ 25
Package Diagrams ............................................................ 26
Document History Page .................................................... 27
Sales, Solutions, and Legal Information ......................... 29
Worldwide Sales and Design Support.......................... 29
Products ....................................................................... 29
Document Number: 001-06431 Rev. *I
N
ot
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Page 2 of 29
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CY14B256K
Pin Configurations
Figure 1. 48-Pin SSOP
V
CAP
NC
A
14
A
12
A
7
A
6
A
5
INT
A
4
NC
NC
NC
V
SS
NC
V
RTCbat
DQ0
A
3
A
2
A
1
A
0
DQ1
DQ2
X
1
X
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
V
CC
NC
HSB
WE
A
13
A
8
A
9
48-SSOP
Top View
(Not To Scale)
39
38
37
36
35
NC
NC
NC
ew
32
31
rN
fo
en
de
d
Pin Definitions
Pin Name
A
0
–A
14
DQ0-DQ7
NC
WE
CE
OE
X
1
X
2
V
RTCcap
V
RTCbat
INT
V
SS
V
CC
HSB
V
CAP
W
E
G
Alt
I/O Type
Input
No Connect
Input
Input
Input
Description
Address Inputs.
Used to select one of the 32,768 bytes of the nvSRAM.
Input or Output
Bidirectional Data I/O lines.
Used as input or output lines depending on operation.
R
ot
Output
Input
N
Power Supply
Power Supply
Output
Ground
Power Supply
Input or Output
Hardware Store Busy (HSB).
When low, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin HIGH if not connected (connection optional).
Power Supply
AutoStore Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
Document Number: 001-06431 Rev. *I
ec
om
No Connects.
This pin is not connected to the die.
Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE high causes the I/O pins to tristate.
Crystal Connection.
Drives crystal on start up.
Crystal Connection for 32.768 kHz Crystal.
Capacitor Supplied Backup RTC Supply Voltage.
(Left unconnected if V
RTCbat
is used)
Battery Supplied Backup RTC Supply Voltage.
(Left unconnected if V
RTCcap
is used)
Interrupt Output.
It is programmed to respond to the clock alarm, the watchdog timer, and the
power monitor. Programmable to either active HIGH (push or pull) or LOW (open drain).
Ground for the Device.
It is connected to ground of the system.
Power Supply Inputs to the Device.
m
D
34
33
30
29
28
27
26
25
es
i
V
SS
NC
V
RTCcap
DQ
6
OE
A
10
CE
DQ7
DQ5
DQ4
DQ3
V
CC
gn
Page 3 of 29
40
A
11
s
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NC
CY14B256K
Device Operation
The CY14B256K nvSRAM consists of two functional
components paired in the same physical cell. The components
are SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM READ and WRITE operations are inhibited. The
CY14B256K supports infinite reads and writes similar to a typical
SRAM. In addition, it provides infinite RECALL operations from
the nonvolatile cells and up to 200K STORE operations.
See the
“Truth Table For SRAM Operations”
on page 23 for a
complete description of read and write modes.
Figure 2. AutoStore Mode
V
CC
V
CAP
V
CAP
V
CC
10k Ohm
WE
SRAM READ
The CY14B256K performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0-14
determines which of the 32,752 data bytes are
accessed. When the READ is initiated by an address transition,
the outputs are valid after a delay of t
AA
(see the section
Figure
8
on page 18). If the READ is initiated by CE or OE, the outputs
are valid at t
ACE
or at t
DOE
, whichever is later (see the section
Figure 9
on page 18). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM WRITE
ec
A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs are stable before entering the
WRITE cycle and must remain stable until either CE or WE goes
HIGH at the end of the cycle. The data on the common I/O pins
DQ
0–7
is written into the memory if the data is valid t
SD
before
the end of a WE controlled WRITE or before the end of a CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common I/O lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
om
m
AutoStore Operation
R
The CY14B256K stores data to nvSRAM using one of the three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256K.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
N
ot
Document Number: 001-06431 Rev. *I
en
de
d
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to
DC Electrical
Characteristics
on page 16 for the size of the V
CAP
. The voltage
on the V
CAP
pin is driven to 5V by a charge pump internal to the
chip. A pull up should be placed on WE to hold it inactive during
power up. This pull up is only effective if the WE signal is tri-state
during power up. Many MPUs tri-state their controls on power up.
Verify this when using the pull up. When the nvSRAM comes out
of power-on-recall, the MPU must be active or the WE held
inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
fo
Hardware STORE (HSB) Operation
The CY14B256K provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B256K conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition, while the STORE
(initiated by any means) is in progress. This pin is externally
pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations, that are in progress when
HSB is driven low by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14B256K continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, t
DELAY
,
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
Page 4 of 29
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