A43L8316A
128K X 16 Bit X 2 Banks Synchronous DRAM
Document Title
128K X 16 Bit X 2 Banks Synchronous DRAM
Revision History
Rev. No.
0.0
1.0
History
Initial issue
Final version release
Issue Date
February 23, 2001
September 29, 2003
Remark
Preliminary
Final
(September, 2003, Version 1.0)
AMIC Technology, Corp.
A43L8316A
128K X 16 Bit X 2 Banks Synchronous DRAM
Features
n
n
n
n
JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Dual banks / Pulse RAS
MRS cycle with address key programs
- CAS Latency (2,3)
- Burst Length (1,2,4,8 & full page)
-
Burst Type (Sequential & Interleave)
n
All inputs are sampled at the positive going edge of the
system clock
n
n
n
n
n
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
16ms refresh period (1K cycle)
50 Pin TSOP (II)
General Description
The A43L8316A is 4,194,304 bits synchronous high data
rate Dynamic RAM organized as 2 X 131,072 words by 16
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
n
TSOP (II)
NC/RFU
VDDQ
VSSQ
DQ
13
DQ
12
DQ
11
DQ
10
UDQM
VDDQ
VSSQ
DQ
15
DQ
14
CKE
VSS
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
A43L8316AV
1
VDD
2
DQ
0
3
DQ
1
4
VSSQ
5
DQ
2
6
DQ
3
7
VDDQ
8
DQ
4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DQ
7
A0
A1
A2
A3
LDQM
VDDQ
A8/AP
VSSQ
VDD
CAS
RAS
DQ
5
DQ
6
WE
CS
BA
(September, 2003, Version 1.0)
1
AMIC Technology, Corp.
VSS
CLK
DQ
9
DQ
8
NC
NC
NC
A7
A6
A5
A4
A43L8316A
Block Diagram
LWE
I/O Control
Data Input Register
Bank Select
LDQM
Row Buffer
Refresh Counter
128K X 16
Row Decoder
Output Buffer
Sense AMP
CLK
Address Register
128K X 16
DQi
LCBR
LRAS
ADD
Column Decoder
Column Buffer
Latency & Burst Length
LRAS
LCAS
LRAS
LCBR
LWE
Programming Register
LDQM
LWCBR
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
(September, 2003, Version 1.0)
2
AMIC Technology, Corp.
A43L8316A
Pin Descriptions
Symbol
CLK
Name
System Clock
Chip Select
Description
Active on the positive going edge to sample all inputs.
Disables or Enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE
Clock Enable
CKE should be enabled at least one clock + tss prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
A0~A8/AP
Address
Row address : RA0~RA8, Column address: CA0~CA7
Selects bank to be activated during row address latch time.
BA
Bank Select Address
Selects band for read/write during column address latch time.
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS
low.
Enables row access & precharge.
Column Address
Strobe
Write Enable
Data Input/Output
Mask
Data Input/Output
Power
Supply/Ground
Data Output
Power/Ground
No Connection
Latches column addresses on the positive going edge of the CLK with
CAS
low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power Supply: +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
CS
RAS
CAS
WE
L(U)DQM
DQ
0-15
VDD/VSS
VDDQ/VSSQ
NC/RFU
(September, 2003, Version 1.0)
3
AMIC Technology, Corp.
A43L8316A
Absolute Maximum Ratings*
Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V
Voltage on VDD supply relative to VSS (VDD, VDDQ )
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V
Storage Temperature (T
STG
) . . . . . . . . . . -55°C to +150°C
Soldering Temperature X Time (T
SLODER
) . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec
Power Dissipation (P
D
) . . . . . . . . . . . . . . . . . . . . . . . . .1W
Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA
*Comments
Permanent device damage may occur if “Absolute
Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended
operating condition.
Exposure to higher than recommended voltage for
extended periods of time could affect device reliability.
Capacitance (T
A
=25°C, f=1MHz)
°
Parameter
Input Capacitance
Symbol
CI1
CI2
A0 to A8, BA
CLK, CKE,
CS
,
RAS
,
CAS
,
WE
,
UDQM, LDQM
DQ0 to DQ15
Condition
Min
2
2
Typ
Max
4
4
Unit
pF
pF
Data Input/Output Capacitance
CI/O
2
6
pF
DC Electrical Characteristics
Recommend operating conditions (Voltage referenced to VSS = 0V)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Output Loading Condition
Symbol
VDD,VDDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
See Figure 1
Max
3.6
VDD+0.3
0.8
-
0.4
5
5
Unit
V
V
V
V
V
µA
µA
Note 1
I
OH
= -2mA
I
OL
= 2mA
Note 2
Note 3
Note
Note:
1. V
IL
(min) = -1.5V AC (pulse width
≤
5ns).
2. Any input 0V
≤
VIN
≤
VDD + 0.3V, all other pins are not under test = 0V
3. Dout is disabled, 0V
≤
Vout
≤
VDD
(September, 2003, Version 1.0)
4
AMIC Technology, Corp.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
