CAT28LV256
256K-Bit CMOS PARALLEL EEPROM
FEATURES
s
3.0V to 3.6V Supply
s
Read Access Times: 200/250/300 ns
s
Low Power CMOS Dissipation:
s
CMOS and TTL Compatible I/O
s
Automatic Page Write Operation:
– Active: 15 mA Max.
– Standby: 150
µ
A Max.
s
Simple Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
s
End of Write Detection:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s
Fast Write Cycle Time:
– Toggle Bit
–
DATA
Polling
s
Hardware and Software Write Protection
s
100,000 Program/Erase Cycles
s
100 Year Data Retention
– 10ms Max.
s
Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E
2
PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
A6–A14
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
32,768 x 8
E
2
PROM
ARRAY
64 BYTE PAGE
REGISTER
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
28LV256 F01
I/O0–I/O7
A0–A5
ADDR. BUFFER
& LATCHES
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-1071, Rev. E
CAT28LV256
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
NC
VCC
WE
A13
A7
A12
A14
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
4 3 2 1 32 31 30
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
29
28
27
26
25
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
TOP VIEW
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
28
27
26
25
24
23
22
21
20
19
18
17
16
15
TSOP Top View (8mm X 13.4mm) (H)
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN FUNCTIONS
Pin Name
A
0
–A
14
I/O
0
–I/O
7
CE
OE
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Pin Name
WE
V
CC
V
SS
NC
Function
Write Enable
3.0 to 3.6 V Supply
Ground
No Connect
Doc. No. MD-1071, Rev. E
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT28LV256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High-Z
High-Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1071, Rev. E
CAT28LV256
D.C. OPERATING CHARACTERISTICS
V
CC
= 3.0V to 3.6V, unless otherwise specified
Limits
Symbol
I
CC
I
SBC(2)
I
LI
I
LO
V
IH(2)
V
IL
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
–1
–5
2
–0.3
2
0.3
Min.
Typ.
Max.
15
150
1
5
V
CC
+0.3
0.6
Units
mA
µA
µA
µA
V
V
V
V
V
I
OH
= –100µA
I
OL
= 1.0mA
Test Conditions
CE
=
OE
= V
IL
,
f = 1/t
RC
min, All I/O’s Open
CE
= V
IHC
,
All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE
= V
IH
A.C. CHARACTERISTICS, Read Cycle
V
CC
= 3.0V to 3.6V, unless otherwise specified
28LV256-20
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ(1)
t
OLZ(1)
t
HZ(1)(3)
t
OHZ(1)(3)
t
OH(1)
Parameter
Read Cycle Time
CE
Access Time
Address Access Time
OE
Access Time
CE
Low to Active Output
OE
Low to Active Output
CE
High to High-Z Output
OE
High to High-Z Output
Output Hold from Address Change
0
0
0
50
50
0
Min.
200
200
200
80
0
0
55
55
0
Max.
28LV256-25
Min.
250
250
250
100
0
0
60
60
Max.
28LV256-30
Min.
300
300
300
110
Max. Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
(3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. MD-1071, Rev. E
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT28LV256
Figure 1. A.C. Testing Input/Output Waveform
(2)
VCC - 0.3V
INPUT PULSE LEVELS
0.0 V
0.6 V
28LV256 F04
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
V
cc
1.8K
DEVICE
UNDER
TEST
1.3K
OUTPUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle
V
CC
= 3.0V to 3.6V, unless otherwise specified
28LV256-20
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW(3)
t
OES
t
OEH
t
WP(3)
t
DS
t
DH
t
INIT(1)
t
BLC(1)(4)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE
Setup Time
CE
Hold Time
CE
Pulse Time
OE
Setup Time
OE
Hold Time
WE
Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
Min.
Max.
10
28LV256-25
Min.
Max.
10
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
28LV256-30
Min.
Max. Units
10
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of
WE.
If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-1071, Rev. E
FPGA/CPLD
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