E123MUX Device
E1/E2/E3 MUX/DEMUX
TXC-03361
DATA SHEET
FEATURES
• Multiplexer/demultiplexer for ITU-T
Recommendations:
G.742 (E2 frame format)
G.751 (E3 frame format)
• Multiplexer/demultiplexer converts:
16 E1s to/from 1 E3 (E13 Skip Mux), or
16 E1s to/from 4 E2s, or
4 E2s to/from 1 E3 (E12/E23 Split Mux)
• Counters for bipolar violations, frame errors and
loss of frame conditions
• E1 digital phase-locked loop circuits with bypass
option
• Test features:
PRBS generator and analyzer for E1 channels
Local/Remote Loopbacks for E1, E2 or E3
channels
Corrupt frame generation for E2 and E3 frames
• E2 and E3 bit error rate indications
• E1 and E3 line side interfaces are selectable as
positive and negative rail or NRZ with external
loss of signal indication on negative input pin.
• Microprocessor input/output bus provides
multiplexed, Intel or Motorola interfaces
• Test access port for IEEE 1149.1 boundary scan
• Single +5 V,
±5
% power supply
• 208-pin plastic quad flat package
DESCRIPTION
The E123MUX is a CMOS VLSI device that provides
the E13 functions needed to multiplex and demultiplex
16 independent E1 signals to and from an E3 signal
that conforms to the ITU-T G.751 Recommendation.
The E1 and E3 signal interfaces can be either dual uni-
polar (rail) or NRZ. Digital phase-locked loop circuits
are provided for the received E1 signals, but they may
be bypassed.
The E123MUX can also be configured to operate as an
E12 or E23 multiplexer and demultiplexer. Sixteen E1
signals can be multiplexed and demultiplexed to and
from four E2 signals that conform to the ITU-T G.742
Recommendation. Alternatively, four E2 signals can
multiplexed and demultiplexed to and from one E3 sig-
nal. The E2 signal interfaces are NRZ only. The
E123MUX uses memory locations for setting control
bits and reporting status information. The status bits
have maskable interrupt control bits.
PRELIMINARY
information documents contain information on products in the sampling, pre-production
or early production phases of the product life cycle. Characteristic data and other specifications are
subject to change. Contact TranSwitch Applications Engineering for current information on this product.
APPLICATIONS
• Single-board E13 multiplexer
• Compact add/drop multiplexer
• DCS and EDSX systems
• CSU/DSU equipment
LINE SIDE
Receive
Transmit
Receive
Transmit
+5V
3
3
TERMINAL SIDE
E3 Clock & Data
E123MUX
E1/E2/E3
MUX/DEMUX
TXC-03361
24
4
5
3
3
Receive E1 Clock & Data
Transmit (x 16 channels)
2
2
2
2
E2 Clock & Data
(x 4 channels)
Receive E2 Clock & Data
(x 4 channels)
Transmit
Microprocessor
Interface selection
and I/O bus
Test
Access
Port
Control and
clock inputs
Document Number:
PRELIMINARY
TXC-03361-MB
Ed. 3, August 1997
Copyright
©
1996-1997 TranSwitch Corporation and Arcus Technology Limited
TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation
•
8 Progress Drive
•
Shelton, CT 06484
•
USA
•
Tel: 203-929-8810
•
Fax: 203-926-9453
E123MUX
TXC-03361
TABLE OF CONTENTS
Section
Page
Block Diagram .....................................................................................................................3
Block Diagram Description ..................................................................................................3
Pin Diagram ........................................................................................................................6
Pin Descriptions ..................................................................................................................7
Absolute Maximum Ratings ..............................................................................................15
Thermal Characteristics ....................................................................................................15
Recommended Operating Conditions and Power Requirements .....................................15
Input, Output and I/O Parameters .....................................................................................16
Timing Characteristics .......................................................................................................18
Operation .....................................................................................................................35-43
Test Access Port ........................................................................................................35
Initialization Sequence ...............................................................................................37
Sample Configurations ...............................................................................................41
Throughput Delays .....................................................................................................43
Memory Map ..................................................................................................................... 44
Memory Map Descriptions .................................................................................................50
Package Information .........................................................................................................76
Ordering Information .........................................................................................................77
Related Products ...............................................................................................................77
Standards Documentation Sources ..................................................................................78
List of Data Sheet Changes ..............................................................................................79
Documentation Update Registration Form* .................................................................85
* Please note that TranSwitch provides documentation for all of its products. Customers who are using
a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department
to receive relevant updated and supplemental documentation as it is issued. They should also contact
the Applications Engineering Department to ensure that they are provided with the latest available in-
formation about the product, especially before undertaking development of new designs incorporating
the product.
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
E123MUX TXC-03361 Block Diagram ..........................................................3
E123MUX TXC-03361 Pin Diagram ..............................................................6
E1 Transmit Input Interface Timing .............................................................18
E12 Transmit Output Interface Timing .........................................................19
E23 Transmit Input Interface Timing ...........................................................20
E3 Transmit Output Interface Timing ...........................................................21
E3 Receive Input Interface Timing ..............................................................22
E23 Receive Output Interface Timing ..........................................................23
E12 Receive Input Interface Timing ............................................................24
E1 Receive Output Interface Timing - PLL Enabled ....................................25
E1 Receive Output Interface Timing - PLL Bypassed .................................26
External Clocks Interface Timing .................................................................27
Boundary Scan Timing ................................................................................28
Multiplex Mode - Microprocessor Read Cycle Timing .................................29
Multiplex Mode - Microprocessor Write Cycle Timing .................................30
Intel Mode - Microprocessor Read Cycle Timing .........................................31
Intel Mode - Microprocessor Write Cycle Timing .........................................32
Motorola Mode - Microprocessor Read Cycle Timing .................................33
Motorola Mode - Microprocessor Write Cycle Timing ..................................34
Boundary Scan Schematic ..........................................................................36
E123MUX TXC-03361 208-pin Plastic Quad Flat Package ........................76
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PRELIMINARY
TXC-03361-MB
Ed. 3, August 1997
E123MUX
TXC-03361
BLOCK DIAGRAM
E12TCKIm (8448 kHz)
Clock
E1 to E2 Multiplexer (Four)
Ch 1
Ch 1
E1 Mux
E1 Mux
I/O
HDB3, LOS
E1TCKn
FIFO
Ch 2
Ch 3
Ch 4
E12
Mux
E12TDm/
E23TDm
E12TCKOm/
E23TCKm
(m = 1-4)
Internal Clock
Frame
Pattern
Alarm Bit
National Bit
AIS GEN
E2AISC
3
Mux 2-4
E1
Ch 1
E2 Mux
E2 Data
and Clock
I/O Block
E2 to E3 Multiplexer
Ch 1
Ch 1
E2 Mux
FIFO
Ch 2
Ch 3
Ch 4
E23
Mux
E3 Mux
I/O
HDB3
E2
Ch 1
E3TDP/E3TNRZ
E3TDN
E3TCKO
E3TCKI
E1TDPn/E1TNRZn
E1TDNn/E1LOSn
(n = 1 - 16)
Internal Clock
Frame
Pattern
Alarm Bit
National Bit
AIS GEN
Transmit
Alarms, Control, Overhead Bits
Microprocessor
Block
Microprocessor
Interface
Receive
E2 to E1 Demultiplexer (Four)
Ch 1
E1RDPn/E1RNRZn
E1RDNn
E1
Demux I/O
HDB3
E3 to E2 Demultiplexer
Ch 1
Ch 1
E2
E2
Demux
FIFO
Ch 1
Ch 2
Ch 3
Ch 4
E32
Demux
E3
Demux
I/O
HDB3
LOS
E3RDP/E3RNRZ
E3RDN/E3LOS
E3RCKI
Ch 1
E1
E1
Demux
FIFO
Ch 1
Ch 2
Ch 3
E2 Data and Clock
E21
Demux
E12RDm/
E23RDm
E12RCKm/
E23RCKm/
E23RGCm
(m = 1-4)
E2
Demux I/O
HDB3
E1RCKn
(n = 1 - 16)
DPLL
Block
Ch 4
Clock
Clock
Frame
SYNC
Alarm Bit
National Bit
AIS Detector
Frame
SYNC
Alarm Bit
National Bit
AIS Detector
System Clock
XCLK
Note: Test Access Port block and Microprocessor Interface lead details are not shown. Please refer to Pin Descriptions section.
Figure 1. E123MUX TXC-03361 Block Diagram
BLOCK DIAGRAM DESCRIPTION
Figure 1 shows a simplified block diagram of the E123MUX and its signal leads. In the transmit direction (mul-
tiplexer direction), the E123MUX multiplexes 16 independent asynchronous E1 signals operating at 2048 kbit/s
into four separate E2 signals operating at 8448 kbit/s. The E1 transmit signal inputs can be in either the dual
rail unipolar HDB3 format (E1TDPn and E1TDNn) or in the NRZ format (E1TNRZn). The rail/NRZ interface
selection is common to both the multiplexer and demultiplexer sections of the chip. The clock edge for clocking
in the data is programmable for either clock (E1TCKn) edge. When the rail interface is selected, the E1 rail sig-
nal interface is monitored for loss of signal using the detect and recovery requirements specified in ITU-T Rec-
ommendation G.775. Loss of signal status information is provided along with a maskable interrupt. In addition,
bipolar violations (BPVs) are counted in 16-bit counters provided for each of the E1 channels. When the NRZ
interface is selected for an E1 channel, an external loss of signal indication from the external line interface unit
can also be provided as an input to the E123MUX on the lead designated as E1TDNn/E1LOSn, to provide sta-
tus information and a maskable interrupt for the microprocessor.
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PRELIMINARY
TXC-03361-MB
Ed. 3, August 1997
E123MUX
TXC-03361
Four E1 framed or unframed asynchronous channels operating at 2048 kbit/s are multiplexed into one E2 sig-
nal, using the frame format specified in ITU-T recommendation G.742. The G.742 format consists of the 848
bits, starting with bit 1 in the frame alignment. The frame alignment pattern is defined as 1111010000. Bit 11 is
defined as a remote alarm, and bit 12 is defined as a spare bit. The remaining bits carry tributary bits and justi-
fication control bits.
The four E12 multiplexers are numbered 1 through 4. Microprocessor access is provided in the transmit direc-
tion in each of the four E1 frame formats for controlling the states of the remote alarm indication bit (bit 11) and
the spare bit (bit 12). Continuous framing errors may also be inserted into each of four frame formats.
The output of the four E12 multiplexers is connected internally to the E23 multiplexer section when the device
is configured for E13 operation. The E2 multiplexed data and clock for the four E12 channels is not provided as
an interface in this mode. However, an external 8448 kHz clock is required to be connected to the E12TCKIm
input for clocking data out from the E12 multiplexer. The E23 section multiplexes each of the four E2 frames
into a single E3 signal using the format specified in ITU-T recommendation G.751. The G.751 format consists
of the 1536 bits, starting with bit 1 in the frame alignment. The frame alignment pattern is defined as
1111010000. Bit 11 is defined as a remote alarm, and bit 12 is defined as a spare bit. The remaining bits carry
tributary bits and justification control bits. A 34368 kHz input clock (E3TCKI) is used to derive the output E3
clock (E3TCKO), which is used to clock out the E3 data. Microprocessor access is provided for controlling the
states of the remote alarm indication bit (bit 11) and the spare bit (bit 12) in the E3 frame format. Continuous
framing errors may also be inserted into the frame format. The output of the E23 multiplexer can be configured
to be either a dual unipolar HDB3 signal or an NRZ signal. The control bit for selecting the HDB3 or NRZ for-
mat is common to the demultiplexer (receive direction). Data (E3TDP/E3TNRZ and E3TDN) is clocked out of
the E123MUX using the E3 clock (E3TCKO) signal, which is derived from the E3 input clock (E3TCKI). A con-
trol bit is provided for clocking out the data on either clock edge.
In the receive direction (demultiplexed direction) from the E3 line, HDB3 or NRZ data (E3RDP/E3RNRZ and
E3RDN/E3LOS) is clocked into the E123MUX using the E3 clock (E3RCKI) signal. The clock edge employed
can be programmed using the microprocessor. The E23 demultiplexer monitors the incoming signal for loss of
signal using the requirements specified in ITU-T recommendation G.775. Bipolar violations are counted in a
16-bit counter. In addition, the E123MUX detects frame alignment using the requirements specified in the
G.751 recommendation, and monitors the line signal for AIS. Besides providing status bits for LOS, AIS, and
LOF, both framing errors and loss of frame events are counted in 8-bit counters. The status bits have maskable
interrupt control bits for enabling and disabling the interrupt for the microprocessor. The remote alarm bit (bit
11), and the national bit (bit 12) in the frame format are monitored for status. A threshold detector is provided
for a bit error rate (BER) measurement. The E3 signal is demultiplexed into four E2 signals, which pass
through 32-bit FIFOs at the output.
When the device is configured as an E13 multiplexer/demultiplexer, the four E2 signals are connected inter-
nally to the four E12 demultiplexers. The E2 signals are available for monitoring using the data lead E23RDm
and gapped clock lead.
Each of the four E2 signals is monitored for frame alignment and AIS, which are provided with status bits and
maskable interrupt control bits. The states of the remote alarm bit (bit 11) and national bit (bit 12) in each of the
four E2 frames are provided as status bits with associated maskable interrupts. A threshold detector is
provided for a bit error rate (BER) measurement. Each of the E12s demultiplexes the E2 frame into four E1
signals. The data is written into 32-bit FIFOs using the internal gapped clock. Each E1 channel has an internal
digital phase-locked loop circuit (DPLL). The receive gapped clock is connected to the digital phase-locked
loop circuit (DPLL) as the reference frequency, along with the 34.368 MHz external system clock (XCLK). The
output of the DPLL is used to clock the data from the E1 receive FIFO, and is also provided as an output
(E1RCKn). Under microprocessor control, either clock edge may be used to clock out the data (E1RDPn/
E1RNRZn and E1RDNn).
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PRELIMINARY
TXC-03361-MB
Ed. 3, August 1997
E123MUX
TXC-03361
The E123MUX can also be configured into hybrid configurations. That is, the device can be configured to pro-
vide four E12 multiplexers and demultiplexers (16 E1 channels to/from four E2 channels), and one E23 multi-
plexer and demultiplexer (four E2 channels to/from one E3 channel). In this configuration, the format of the
data from the four multiplexers and demultiplexers at the E2 level is NRZ only. In the multiplex direction, the
data (E12TDm) from the four sections is clocked out by the E2 clocks (E12TCKOm). The NRZ data input
(E23TDn) to the E23 multiplexer is clocked in by the E2 clocks (E23TCKm). The clock edges used for clocking
in and out data from the E23 section are programmable.
In the demultiplex direction, four E23 gapped output clocks are provided on leads E23RGCm. E2 data
(E23RDm) is clocked out of the internal FIFO by the receive input clock (E23RCKm). It is assumed that exter-
nal DPLLs will be used in this configuration to provide a symmetrical clock, and that the outputs of the DPLLs
are connected to the E23RCKm leads for E2 operation. The receive data input to the four E12 demultiplexers
consists of data (E12RDm) and clock (E12RCKm).
If an E23 demultiplexer is connected to the E12 demultiplexer to provide E3 to E1 demultiplexing, the E23
receive gapped clock lead (E23RGCm) is connected to the E23 receive input clock (E23RCKm) and the E12
receive input clock (E12RCKm). The E23 data leads (E23RDm) are connected to the E12 receive data leads
(E12RDm). The clock edges used for clocking data into and out of the E12 sections are programmable.
The E123MUX provides a number of testing features, including an E1 PRBS generator and analyzer. The
PRBS sequence is a 2
15
-1 polynomial, and the sequence corresponds to the sequence specified in the ITU-T
O-151 recommendation. The E1 transmit channel to be used for inserting the PRBS pattern is programmable.
The E1 receive channel to be analyzed is also programmable, and is independent of the channel selected in
the transmit direction. Only one channel at a time is programmable for PRBS testing in each direction.
The E123MUX also supports individual E1 remote loopbacks, E2 local and remote loopbacks, and E3 local
and remote loopbacks. Remote loopback enables the receive clock and data leads to be looped back as trans-
mit clock and data in the upstream direction.
For device testing, both boundary scan and an option to force all bidirectional outputs to a high impedance
state for board testing are provided. The boundary scan feature conforms to the IEEE 1149.1 standard.
The microprocessor interface supports a multiplexed 8-bit address/data bus, an Intel-compatible split bus or a
Motorola-compatible split bus. The split bus has 8 address bits and 8 data bits. Interrupt capability is also pro-
vided, with the ability to mask an active alarm status from causing an interrupt.
-5-
PRELIMINARY
TXC-03361-MB
Ed. 3, August 1997
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