Features
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7.4 SPECint95, 6.1 SPECfp95 @ 300 MHz (estimated)
Superscalar (3 instructions per clock peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On Chip Debug Support
P
D
typical = 3.5 Watts (266 MHz), Full Operating Conditions
Nap, Doze and Sleep Modes for Power Savings
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4G byte Direct Addressing Range
Pipelined Single/double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
f
int
max = 300 MHz
f
bus
max = 75 MHz
Compatible CMOS Input / TTL Output
Screening / Quality / Packaging
This product is manufactured in full compliance with:
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CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards
CBGA 255: Upscreenings based upon ATMEL-Grenoble standards
Full Military Temperature Range (T
c
= -55°C, T
c
= +125°C)
IndustriaL Temperature Range (T
c
= -40°C, T
c
= +110°C)
Internal // I/O Power Supply = 2.5 ± 5% // 3.3V ± 5%
255 Pin CBGA Package and 255 Pin CBGA with SCI (CI-CGA) Package
PowerPC
603e™ RISC
Microprocessor
Family
PID7t-603e
Specification
TSPC603R
Description
The PID7t-603e implementation of PowerPC603e (after named 603r) is a low-power
implementation of reduced instruction set computer (RISC) microprocessors Pow-
erPC family. The 603r implements 32-bit effective addresses, integer data types of
8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603r is a low-power 2.5/3.3-volt design and provides four software controllable
power-saving modes.
The 603r is a superscalar processor capable of issuing and retiring as many as three
instructions per clock. Instructions can execute out of order for increased perfor-
mance; however, the 603r makes completion appear sequential. The 603r integrates
five execution units and is able to execute five instructions in parallel.
The 603r provides independent on-chip, 16K byte, four-way set-associative, physi-
cally addressed caches for instructions and data and on-chip instruction and data
memory management units (MMUs). The MMUs contain 64-entry, two-way set-asso-
ciative, data and instruction translation look aside buffers that provide support for
demand-paged virtual memory address translation and variable-sized block
translation.
The 603r has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r
interface protocol allows multiple masters to complete for system resources through a
central external arbiter. The 603r supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/O.
Rev. 2125A–12/01
1
The 603r uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compatibility with TTL
devices.
The 603r integrates in system testability and debugging features through JTAG boundary-scan capability.
G suffix
CBGA 255
Ceramic Ball Grid Array
GS suffix
CI-CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
General
Description
Figure 1.
Block Diagram
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b
address
64b
data
System Bus
2
TSPC603R
2125A–12/01
TSPC603R
Introduction
The 603r is a low-power implementation of the PowerPC microprocessor family of reduced
instruction set computer (RISC) microprocessors. The 603r implements the 32-bit portion of
the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8,
16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC micropro-
cessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and
other features required to complete the 64-bit architecture.
The 603r provides four software controllable power-saving modes. Three of the modes (the
nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of
power dissipated by the processor. The fourth is a dynamic power management mode that
causes the functional units in the 603r to automatically enter a low-power mode when the
functional units are idle without affecting operational performance, software execution, or any
external hardware.
The 603r is a superscalar processor capable of issuing and retiring as many as three instruc-
tions per clock. Instructions can execute out of order for increased performance; however, the
603r makes completion appear sequential.
The 603e integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a
branch processing unit (BPU), a load/store unit (LSU) and a system register unit (SRU). The
ability to execute five instructions in parallel and the use of simple instructions with rapid exe-
cution times yield high efficiency and throughput for 603r-based systems. Most integer
instructions execute in one clock cycle. The FPU is pipelined so a single-precision multi-
ply-add instruction can be issued every clock cycle.
The 603r provides independent on-chip, 16K byte, four-way set-associative, physically
addressed caches for instructions and data and on-chip instruction and data memory manage-
ment units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and
instruction translation look aside buffers (DTLB and ITLB) that provide support for
demand-paged virtual memory address translation and variable-sized block translation. The
TLBs and caches use a least recently used (LRU) replacement algorithm. The 603r also sup-
ports block address translation through the use of two independent instruction and data block
address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are
compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and
BAT array, the BAT translation takes priority.
The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r interface
protocol allows multiple masters to compete for system resources through a central external
arbiter. The 603r provides a three-state coherency protocol that supports the exclusive, modi-
fied, and invalid cache states. This protocol as a compatible subset of the MESI
(modified/exclusive/shared/invalid) four-state protocol and operates coherently in systems that
contain four-state caches. The 603r supports single-beat and burst data transfers for memory
accesses, and supports memory-mapped I/O.
The 603r uses an advanced, 0.29 µm 5 metal layer CMOS process technology and maintains
full interface compatibility with TTL devices.
3
2125A–12/01
Pin Assignments
CBGA 255 and CI-CGA
255 Packages
Figure 2 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA pack-
ages. The direction of the top surface view is shown by the side profile of the packages.
Figure 2.
CBGA 255 and CI–CGA 255 Top View
Pin matrix top view
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Substrate Assembly
Die
View
CBGA 255
Encapsulant
CI±CGA 255
Not to scale
4
TSPC603R
2125A–12/01
TSPC603R
Pinout Listing
Table 1.
Power and Ground Pins
VDD
2
PLL (AVDD)
Internal Logic
Output Drivers
A10
F06, F08, F09, F11, G07, G10, H06, H08, H09, H11,
J06, J08, J09, J11, K07, K10, L06, L08, L09, L11
C07, E05, E07, E10, E12, G03, G05, G12, G14, K03,
K05, K12, K14, M05, M07, M10, M12, P07, P10
C05, C12, E03, E06, E08, E09, E11, E14, F05, F07,
F10, F12, G06, G08, G09, G11, H05, H07, H10, H12,
J05, J07, J10, J12, K06, K08, K09, K11, L05, L07, L10,
L12, M03, M06, M08, M09, M11, M14, P05, P12
GND
Table 2.
Signal Pinout Listing
Signal Name
A[0-31]
AACK
ABB
AP[0-3]
APE
ARTRY
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLK_OUT
CSE[0-1]
DBB
DBG
DBDIS
DBWO
DH[0-31]
DL[0-31]
DP[0-7]
DPE
DRTRY
GBL
HRESET
INT
CBGA Pin Number
C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13, G02, E15, H01, E16, H02,
F13, J01, F14, J02, F15, H03, F16, F04, G13, K01, G15, K02, H16, M01, J15, P01
L02
K04
C01, B04, B03, B02
A04
J04
L01
B06
E01
D08
A06
D07
B01, B05
J14
N01
H15
G04
P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P09, N09, T10, R09,
T09, P08, N08, R08, T08, N07, R07, T07, P06, N06, R06, T06, R05, N05, T05, T04
K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15,
R16, R14, T14, N10, P13, N12, T13, P03, N03, N04, R03, T01, T02, P04, T03, R04
M02, L03, N02, L04, R01, P02, M04, R02
A05
G16
F01
A07
B15
Active
High
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
-
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
Low
Low
I/O
I/O
Input
I/O
I/O
Output
I/O
Input
Output
Output
Input
Output
Output
Output
I/O
Input
Input
Input
I/O
I/O
I/O
Output
Input
I/O
Input
Input
5
2125A–12/01
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