IDT77V7101
Gigabit Ethernet Serdes Transceiver
PARA LLEL TO
SERIAL
INPUT D ATA
LATC HES
Datasheet
b
TX C G [9:0]
T X S E R IA L D A T A
DRIVER
TX P
TX N
TC L K
P L L C AP 1
P L L C AP 2
SDTSEL
SDT
125M H z
T X C LO C K
1,250M H z
CLOCK
M U L TIP L IE R
PLL
E N AB L E O P
S IG N AL
DETECT
E W R AP
E N A B LE
OUTPU T DATA
LATC HES &
DRIVER S
EQUSEL
SERIAL TO
PARA LLEL
R E -T IM E D R X
S E R IA L D A T A
RX CLO CK &
D AT A
RECO VERY
1
0
R X C G [9:0]
R X S E R IA L D A T A
RX
E Q U AL IZ E R
RXP
RXN
1,250M H z
RECO VERED
R X C LO C K
125M H z
R C L K [1]
R C L K [0]
62.5M H z (V 7101 )
125M H z (V 711 1)
RX CLO CK
D IV ID E R
COM DET
ENDET
COM M A
DETECT
R E -S Y N C
Figure 2. IDT77V7101 Internal Block Diagram
Functional Description
Overview
Figure 1 shows a block diagram of a typical application. The
parallel interface connects to a Physical Coding Sublayer (PCS) chip.
The serial inputs and outputs connect directly to a fiber optic module
for optical transmission.
Figure 2 shows an internal block diagram of the IDT77V7101. The
TXCG[9:0] inputs receive parallel 10-bit transmit code groups,
already encoded in 8B/10B format by the PCS chip. The code groups
are latched on the rising edges of the incoming 125MHz reference
clock (TCLK). Then they are serialized, and the bit stream is retimed
by an internal PLL that multiplies TCLK up to 1250MHz. This data
stream is transmitted through PECL drivers into the cable or fiber optic
module.
The 77V7101 receives serial data from the fiber optic module. It
deserializes the data into 10-bit receive code groups, and recovers
a receive clock (RCLK) from the data stream. RCLK is used to clock-
out the receive code groups to the PCS chip.
RCLK is output at 62.5MHz in two complementary phases as
RCLK[0] and RCLK[1]. RCLK[0] and RCLK[1] are used to clock out
alternating code groups.
A Signal Detect I/O pin has been provided. For fiber optic media,
it can be configured as an input, allowing the fiber module to perform
signal detection.
2
Transmit Clock (TCLK)
The user-supplied 125MHz transmit reference clock (TCLK) is
used for several functions. As the transmit code group clock, its rising
edges directly strobe the 10-bit input data latch to sample the transmit
code group bus, TXCG[9:0]. Therefore, its edges must be properly
aligned to the incoming parallel transmit data.
TCLK also serves as the frequency reference for the Transmit PLL
Clock Multiplier, which uses it to synthesize the internal clock signals
necessary for 1.25 Gbps signaling.
Transmit Data Path
It is assumed that the original 8-bit user data to be transmitted has
already been 8B/10B-encoded into 10-bit transmit code groups by
external PCS logic before being sent to the IDT77V7101 for
transmission. The incoming code groups are received on the Transmit
Code Group bus, TXCG[9:0], and are sampled on the rising edges
of TCLK by the input data latch. Figure 6 shows the timing relationship
between the clock and the parallel data, and the “AC Electrical
Characteristics” section shows the timing requirements for these
signals.
The parallel transmit data is sent to the parallel-to-serial converter.
This uses the internal clock signals synthesized by the transmit PLL
to convert the 10-bit transmit data from parallel to serial format, and
to retime each bit at 1250MHz. The least significant bit TXCG[0] is
IDT77V7101
Gigabit Ethernet Serdes Transceiver
Datasheet
transmitted first.
The Transmit Line Driver transmits the serial data in differential
form onto the transmit half of the chosen medium. The Line Driver can
connect directly to copper media such as 150Ω twinax cable (through
DC-blocking capacitors), or through a fiber optic transceiver module
to fiber optic cable.
The Line Driver is a source-follower that provides a voltage-mode
differential PECL-level-compatible output. It has a differential source
impedance of approximately 30Ω. ENABLEOP must be held to a logic
high level for normal operation. When ENABLEOP is held low, the
Line Driver output is set to a high impedance state.
Refer to the “Medium Attachment” section below for more information
on connecting the line driver to various media.
Receive Equalization
The 77V7101/7111 has an equalization circuit at the receiver input
to compensate the signal distortion caused by unequalized cable. For
operation over short cables or long internally equalized cables, the
equalizer can be either enabled or disabled.
Users may wish to disable it in cases where crosstalk or reflections
rather than electrical line length are the major causes of signal
impairment, such as when the serial link runs through a crowded
backplane or poorly matched connector rather than a long unequalized
cable. Doing so can improve the tolerance of these impairments. The
equalizer can also be disabled for the same reason when interfacing
to fiber optic transceivers or to short or internally-equalized cables.
each occurrence of a comma+ causes realignment of the bit positions
of the received comma+ code group to match the standard 8B/10B
format. Realignment may be achieved by dropping bits from the data
stream when necessary. Comma+ characters are always clocked out
by the rising edge of RCLK[1]. In the case of the 77V7101 this may
entail stretching RCLK[1:0] half a cycle (nominally 8ns). Subsequent
code groups retain this bit and clock alignment unless shifted by
errors. If ENDET=0, realignment and clock stretching are disabled.
The COMDET output is an indicator for the detection of comma+
characters. When ENDET is high and a comma+ character is
detected, COMDET will go high for half an RCLK period, following the
rising edge of RCLK[0]. Otherwise, it will remain low.
Proper operation of COMDET, RCLK[1:0], and the code group
alignment function requires that comma+ characters not be received
back-to-back, as per standard 8B/10B encoding.
Signal Detect
The Signal Detect pin SDT is a bi-directional pin controlled by
SDTSEL. When STDSEL is high, SDT is an output that remains high
when the receive signal amplitude exceeds the Signal Detect threshold
V
SD
, and receive data will be output normally at RXCG[9:0]. (Note
that this does not indicate that a compliant 1000BASE-X signal is being
received.) A receive signal amplitude below the threshold causes the
SDT output to remain low, and the RXCG[9:0] outputs to all be forced
to logic 1. This helps prevent the generation of random data at the
receiver outputs in the absence of valid incoming data.
When SDTSEL is low, SDT becomes a PECL input to allow
external devices such as fiber optic modules to perform the Signal
Detect function. Signal detection should cause the external device to
drive SDT to PECL logic 1, while insufficient signal amplitude should
drive SDT to PECL logic 0. As before, a logic 0 at SDT will cause
RXCG[9:0] outputs to all be forced to logic 1.
Clock Recovery
After the serial input signal has passed through the front end’s
equalizing amplifier, a receive clock must be recovered with which to
sample the incoming data stream. Clock recovery is automatic, with
no user intervention such as PLL training necessary. The internal
Receive PLL locks the phase of its VCO to that of the incoming data
to produce a bit-clock. This bit-clock is then divided down to become
the internal 125MHz code-group clock(ICLK). Finally, the recovered
receive clock is output as complementary signals (180° out of phase
with each other) at RCLK[0] and RCLK[1] at 62.5MHz in the 77V7101,
and at 125MHz in the 77V7111. In the 77V7101, the 62.5MHz
RCLK[0] and RCLK[1] signals are used to clock out alternating
125MHz code groups. In the 77V7111, 125MHz RCLK[1] or RCLK[0]
signals provide rising-edge or falling-edge clocking of all receive
code groups, respectively.
Internal Loopback
Loopback mode permits testing most of the internal circuitry without
using an external medium, and is enabled by holding EWRAP high.
Transmit code groups sent to the TXCG[9:0] inputs are processed
normally by the transmit circuitry, then looped back through the
receive circuitry to the RXCG[9:0] outputs as if they were incoming
serial data. At the loopback point, transmit serial data is diverted from
before the Line Driver, and replaces the equalizer output as the input
to the clock and data recovery circuits. Nearly all the internal circuits
except for the Line Driver and Receive Equalizer are exercised, with
all internal Serializer, Deserializer, and clock functions occurring at
their normal rates.
Loopback mode holds the Line Driver output at PECL logic 1. For
normal operation, EWRAP must be held low.
Data Recovery
Following equalization and buffering, the receive serial data
stream is retimed by the recovered bit-clock, then converted from
serial to parallel form using both bit- and code-group-clocks. Parallel
receive data is clocked into the output data latch by the internal
125MHz code-group-clock, and output at the Receive Code Group
bus, RXCG[9:0]. RCLK[1:0] are used to clock out the data from
RXCG[9:0] as described in “Clock Recovery” above.
Medium Attachment
(Serial Interface)
Figure 3 shows a typical method of connecting either fiber optic
links. In this case 150Ω bias resistors are connected from TXP and
TXN to ground. AC-coupling of transmitter output to cable is used, as
required by IEEE 802.3z. The optional series resistors RSER may
be added to help absorb reflections due to mismatched loads. Typical
Code Group Alignment
A code group alignment function detects the presence of comma+
characters (0011111xxx) in the receive data stream. If ENDET=1,
3
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