PRELIMINARY
BU-65565
MIL-STD-1553 PMC CARD
DESCRIPTION.
The BU-65565 is a single-channel or multi-
channel MIL-STD-1553 PMC card. The BU-65565 includes
one to four dual redundant 1553 channels on a convection-
cooled or conduction-cooled card.
The design of the BU-65565 leverages the Enhanced Mini-
ACE. Each channel may be independently programmed for
BC, RT, Monitor, or RT/Monitor mode.
Advanced architectural features of the Enhanced Mini-ACE
include a highly autonomous bus controller, an RT providing
a wide variety of buffering options, and a selective message
monitor. Each Enhanced Mini-ACE channel incorporates
64K words of RAM, and utilizes 3.3 volt logic to reduce
power consumption.
The conduction-cooled version of the card includes a black
anodized aluminum plate, thermal vias connected to chassis
ground, along with a chassis ground plane to provide
improved thermal conduction.
The BU-65565 is supported by free software, including a
C++ library and VxWorks driver. The library and driver
comprise a suite of C function calls that serves to offload a
great deal of low-level tasks from the application
programmer. This software supports all of the Enhanced
Mini-ACE’s advanced architectural features.
FEATURES
•
•
•
•
•
•
32-bit/33 MHz PMC Card
One to Four Dual Redundant
MIL-STD-1553 Channels
Conduction or Convection
Cooled
Enhanced Mini-ACE BC/RT/MT
Architecture
64K-word RAM per Channel
Highly Autonomous Bus
Controller Architecture
-
Asynchronous Messages
-
Message Timing Control
-
Bulk Data Transfers
-
Data Block Double Buffering
-
Retries and Bus Switching
RT Buffering Options
-
Single Buffering
-
Double Buffering
-
Subaddress Circular
Buffering
-
Global Circular Buffering
Selective Message Monitor
Supports PCI Interrupts
VxWorks Software Driver
•
•
•
•
BU-61864
BU-61864
32-bit,
33 MHz
PCIbus
PCI
Bridge
BU-61864
1 to 4
MIL-STD-1553
Buses
BU-61864
Figure 1. Block Diagram
1
PARAMETER
Table 1. BU-65565 Specification Table
MIN
TYP
MAX
UNITS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
+3.3V
+5 V
RECEIVER
Input Impedance, Transformer Coupled (Notes
1-3)
Threshold Voltage, Transformer Coupled
Common Mode Voltage (Note 4)
TRANSMITTER
Differential Output Voltage
Transformer Coupled Across 70 ohms
Output Offset Voltage, Transformer Coupled
Across 70 ohms
Rise/Fall Time
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances (Note 9)
+3.3 V (logic power)
+5 V (RAM and transceiver power)
Current Drain
BU-65565X1
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65565X2
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65565X3
+5 V
• Idle
• 25% Duty Transmitter Cycle
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
BU-65565X4
+5 V
• Idle
• 25% Duty Transmitter Cycle
2
-0.3
-0.3
1.000
0.200
6.0
7.0
V
V
kohm
0.860
10
V
P-P
V
PEAK
18
-250
100
20
150
150
27
250
300
V
P-P
mV
PEAK
ns
3.0
4.5
3.3
5.0
3.6
5.5
V
V
100
210
320
540
80
mA
mA
mA
mA
mA
200
420
640
1.08
120
mA
mA
mA
A
mA
300
630
960
1.62
160
mA
mA
mA
A
mA
400
840
mA
mA
PARAMETER
Table 1. BU-65565 Specification Table
MIN
TYP
MAX
1.28
2.16
200
UNITS
A
A
mA
• 50% Duty Transmitter Cycle
• 100% Duty Transmitter Cycle
+3.3 V (Logic)
Power Dissipation
BU-65565X1
Idle
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65565X2
Idle
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65565X3
Idle
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65565X4
Idle
25% Duty Transmitter Cycle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
1553 MESSAGE TIMING
Completion of CPU Write (BC Start)-to-Start of
Next Message (Non-enhanced BC mode)
BC Intermessage Gap – (Note 5)
Non-Enhanced (Mini-ACE compatible) BC
mode
Enhanced BC mode (Note 6)
BC/RT/MT Response Timeout (Note 7)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time (mid-parity to mid-sync)
(Note 8)
Transmitter Watchdog Timeout
THERMAL
Operating Junction Temperature
Storage Temperature
PHYSICAL CHARACTERISTICS
Size
3
0.84
1.12
1.41
1.98
1.53
2.10
2.67
3.81
2.23
3.08
3.93
5.64
2.92
4.06
5.20
7.47
2.5
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
µs
µs
µs
9.5
10.0 to
10.5
17.5
21.5
49.5
127
4
18.5
22.5
50.5
129.5
19.5
23.5
51.5
131
7
µs
µs
µs
µs
µs
µs
660.5
-55
-65
150
150
°C
°C
mm
149 X 74
PARAMETER
Table 1. BU-65565 Specification Table
MIN
TYP
5.87 X 2.91
MAX
UNITS
(in)
oz
(g)
Weight
TBD
(TBD)
Notes:
Notes 1 through 3 are applicable to the Input Impedance specification:
The specifications are applicable for both unpowered and powered conditions.
The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The
applicable frequency range is 75 kHz to 1 MHz
(3) Minimum impedance is guaranteed over the operating range, but is not tested.
(4) Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to
pins of the isolation transformer on the stub side (transformer coupled), and referenced to
signal.
(5) Typical value for minimum intermessage gap time. Under software control, this may
be lengthened to 65,535
µs
- message time, in increments of 1
µs.
If ENHANCED CPU
ACCESS, bit 14 of Configuration Register #6, is set to logic “1”, then host accesses during
BC Start-of-Message (SOM) and End-of-Message (EOM) transfer sequences could have
the effect of lengthening the intermessage gap time. For each host access during an SOM
or EOM sequence, the intermessage gap time will be lengthened by 6 clock cycles. Since
there are 7 internal transfers during SOM, and 5 during EOM, this could theoretically
lengthen the intermessage gap by up to 72 clock cycles; i.e., up to 7.2
µs
with a 10 MHz
clock, 6.0
µs
with a 12 MHz clock, 4.5
µs
with a 16 MHz clock, or 3.6
µs
at MHz clock.
(6) For enhanced BC mode, the typical value for intermessage gap time is approximately 10
clock cycles longer than for the non-enhanced BC mode. That is, an addition of 1.0
µs
at
10 MHz, 833 ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(7) Software programmable (4 options). Includes RT-to-RT Timeout (measured mid parity of
transmit Command Word to mid-sync of Transmitting RT Status Word).
(8)
Measured from mid-parity crossing of Command Word to mid-sync crossing of RT's
Status Word.
(9) The standard BU-5565 board requires +3.3 volt and +5 volt power. For applications where +3.3 volts is
not available, DDC is able to supply a non-standard version of the BU-65565 card requiring only +5
volts (consult factory).
(1)
(2)
INTRODUCTION
The BU-65565 is a single-channel or multi-channel MIL-STD-1553 PMC card.
The BU-65565 is available with one to four dual redundant 1553 channels on a
convection-cooled or conduction-cooled card.
The design of the BU-65565 leverages the BU-61864 Enhanced Mini-ACE. Each
channel may be independently programmed for BC, RT, Monitor, or RT/Monitor
mode.
Advanced architectural features of the Enhanced Mini-ACE include a highly
autonomous bus controller, an RT providing a wide variety of buffering options,
and a selective message monitor. Each Enhanced Mini-ACE channel
incorporates 3.3 volt logic to reduce power consumption and 64K words of RAM.
4
The conduction-cooled version of the card includes a black anodized aluminum
plate, thermal vias connected to chassis ground, along with a chassis ground
plane to provide improved thermal conduction.
The BU-65565 is supported by free software, including a C++ library and a
VxWorks driver. The library and driver comprise a suite of C function calls that
serves to offload a great deal of low-level tasks from the application programmer.
This software supports all of the Enhanced Mini-ACE’s advanced architectural
features.
ENHANCED MINI-ACE
The BU-65565 PMC card incorporates a PCI bridge, along with between one and
four of DDC’s BU-61564G3 Enhanced Mini-ACE hybrids. Each Enhanced Mini-
ACE comprises a complete, independent interface between the PCI bridge and a
MIL-STD-1553 bus. The Enhanced Mini-ACE hybrids provide software
compatibility with the DDC’s older generation ACE and Mini-ACE (Plus)
terminals.
The BU-61564 Enhanced Mini-ACE provides complete multiprotocol support of
MIL-STD-1553A/B/McAir and STANAG 3838. These hybrids include dual
transceiver; along with protocol, host interface, memory management logic; and
64K X 16 of RAM. There is built-in parity checking for this RAM.
The Enhanced Mini-ACEs include a 5V, voltage source transceiver for improved
line driving capability, with options for MIL-STD-1760 compliance (20 V
P-P
minimum transmitter voltage) or McAir compatibility (consult factory). As a means
of reducing power consumption, the Mini-ACEs’ logic is powered by 3.3V.
One of the new salient features of the Enhanced Mini-ACE is its new bus
controller architecture. The Enhanced BC’s highly autonomous message
sequence control engine provides a means for offloading the host processor for
implementing multi-frame message scheduling, message retry and bus switching
schemes, data double buffering, and asynchronous message insertion. In
addition, the Enhanced BC mode includes 8 general purpose flag bits, a general
purpose queue, and user-defined interrupts, for the purpose of performing
messaging to the host processor.
Another important feature for the Enhanced Mini-ACE is the incorporation of a
fully autonomous built-in self-test. This test provides comprehensive testing of
the internal protocol logic. A separate test verifies the operation of the Enhanced
Mini-ACE’s internal RAM. Since the self-tests are fully autonomous, they
eliminate the need for the host to write and read stimulus and response vectors.
The Enhanced Mini-ACE RT offers the choice of single, double, and circular
buffering for individual subaddresses or a global circular buffering option for
multiple (or all) receive subaddresses, a 50% rollover interrupt for circular
buffers, an interrupt status queue for logging up to 32 interrupt events, and an
option to automatically initialize to RT mode with the Busy bit set.
5
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